Hi all,I'm doing a new board in which we have chosen to use Qsys and in particular a PCIe Requester/Completer. I'm at preliminary phase and reading the user guide it is state a lot of time that 125MHz (used for application logic) and 50MHz (used for recalibration purpoise) shall be derived by a free running clock different from the 100 Mhz ref clock. Is this a must? I cannot really understand why.. Moreover on the board electrical schematic it is exactly that 100 Mhz that is distributed to FPGA PCIe ref clock, to a PPC that use PCIe and also to other clock input specific pin of FPGA.. (Of course an apposite clock buffer is used).
I can't tell you the reason for the free running clock but I can tell you that the only reference design that I've got to work uses a free running clock. The Altera PCIe implementation is proving horribly difficult to use, so I wouldn't take any shortcuts.
The PLD_CLK is derived from the Link, i.e. this passes through Lock to Reference to Lock to Data, Hence during link training and transceiver calibration the PLD_CLK may not be stable yet. Hence the reconfig_clk, required for transceiver offset calibration, and the fixedclk required for speed negotiation, must be supplied by a seperate clock that is stable at device power-up.# Note that in "Figure 7-1. Internal Reset Modules in the Hard IP Implementation"of the PCIe User Guide (page 178), the shown "free_running_clock 100MHz" doesn't actually need to be 100MHz, as it is being used as the source for the PLL, any free running clock frequency can be used. Simple modify the PLL settings to match your alternative free running clock frequency. User Guide Link given below: http://www.altera.com/literature/ug/ug_pci_express.pdf
Ok, it was only some nomenclature.I think of about Clock Ref as the specific pin of the FPGA that can feed the transceiver block. That's clock will be always present and it is from it (routed also to another global pin of the FPGA) that I enter in a PLL that derive 125MHz and 50Mhz. All shall work. Thx for suggestions