FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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PCIE Address Translation

Honored Contributor II

The translation registers in the PCIe controller, which translates the requests from the SGDMA controller to PCIe 64 bit address bus requests, and hence, memory accesse requests in the CPU memory.  

If they are set wrong, we may not be doing DMA transfers to the physical address . 



It looks like the A2P_ADDR_SPACE0 field should be set to 0x01. 



Can you please let me know if this configuration is right?
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