Hi,I'm using SOPC Builder to generate PCIE Hard IP, is there a way to access the Configuration Space Register through Avalon-MM port? Thank you. zeahr
HiI have the same question, I'm using the QSyS to generate PCIE Hard IP, is there a way to access the Configuration Space Register through Avalon-MM port employing the NIOS? Thanks Mario
For Avalon-MM, only host PC (root port) driver can do a configuration read type 1 to the endpointin order to access the Configuration Space registers. No any special reason.
Configuration Space Register and AVMM Control and Status Register are two different things.CRA module is only for accessing our PCI Express's Avalon-MM bridge control and status registers (not the PCIe Configuration Space Register). From Table 5-11 of Cyclone V AvMM PCIe User Guide, this address range is targetting the PCIe Interrupt registers. Most of the value will be "0" when read back when PCIe interrupt is not enabled.
Dear skbehAbout this topic, in the “IP Compiler for PCI Express User Guide”, page 4-3(61) says "The Avalon-MM PCIe reconfig bus which can access any read-only configuration space register". In page 5-38(124) mention the chapter 13, where in table 13-1 shows the configuration space register. So I understand that the reconfig bus can access the configuration space; but it is accessed only by the IP, so the use of the QSYS is not directly. Is that true? In the case specific of the reconfiguration, it implies Dynamic Reconfiguration, so do you know what are the considerations/things I will need in order to employ that to access the PCI EXPRESS Configuration Space Register? Thanks Mario
It is true, the use of the QSYS is not directly.Qsys can access the CRA, but not the configuration space register because it's not reside within the CRA address range.
To use the dynamic reconfiguration block, firstly the PCIe Reconfig option on the System Settings page needs to enable.But the reconfig block is only available when the PCIe core is instantiated in Megawizard, it's not available in Qsys.