PCIE Gen4x16 example design

[10]

Hi,

The downstream component is backpressing by deasserting ready, but upstream component cant be backpressed.

can you please clarify the below questions:
1.Testcase flow of PCIe BFM. How to execute different tests?(Which
Modules need to look )

2.Need procedure for Testing Memory write and
Read (32- and 64-bit address) TLP's.

3.How to configure the Descriptor
for DMA modes(Write and Read) in PCIE RC BFM?

Thanks in Advance
Indirapriya

[Rahul_S_Intel1 · Accepted solution]

Hi ,

 The information avaialble for the above is from the below user guide .

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-ptile-pcie-avst.pdf

Kindly requesting to refer the UG