PCIE HIP Register Creation in the App layer?

Altera_Forum · ‎11-21-2013

Hi everybody!

I'm using the example 'PCIe HIP for Avalon ST' Generation 1, 4 Lanes, provided by Altera which can be found in a similar directory as mine C:\altera\13.1\ip\altera\altera_pcie\altera_pcie_hip_ast_ed\example_design\cv\ pcie_de_gen1_x4_ast64.qsys . Once it is compiled, it can easily add new registers in the file ‘altpcierd_reg_access.v‘ . Just modifying the case loop seen in line 195.

case (reg_rd_addr_reg[7:0])

{MISC, WRITE_DMA_STATUS_REG_HI}: reg_rd_data <= write_dma_status_reg[63:32];

{MISC, WRITE_DMA_STATUS_REG_LO}: reg_rd_data <= write_dma_status_reg[31:0];

{MISC, READ_DMA_STATUS_REG_HI} : reg_rd_data <= read_dma_status_reg[63:32];

{MISC, READ_DMA_STATUS_REG_LO} : reg_rd_data <= read_dma_status_reg[31:0];

{ERR_STATUS, 4'h0} : reg_rd_data <= err_status_reg;

{DMA_WRITE_PRG, 4'h0},

{DMA_WRITE_PRG, 4'h4},

{DMA_WRITE_PRG, 4'h8},

{DMA_WRITE_PRG, 4'hC} : reg_rd_data <= dma_wr_prg_rddata_reg;

{DMA_READ_PRG, 4'h0},

{DMA_READ_PRG, 4'h4},

{DMA_READ_PRG, 4'h8},

{DMA_READ_PRG, 4'hC} : reg_rd_data <= dma_rd_prg_rddata_reg;

// my new register : reg_rd_data <= what_I_want_2_send;

default : reg_rd_data <= 32'h0;

endcase

This new register can be read by a host computer, but not modified, so for constants is perfect, but not data which should be modified... so has anyone any idea about how to create a register which can be modified? and how to use the DMA?

I am using a Cyclone V 5CGXFC7D7F31C8ES in a own board designed and it is not possible to use the other example for Avalon MM. thanks for your time.

Regards,

David