FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

PCIE errors

CLeon14
Beginner
421 Views

I am compiling a Q19.4 with 2 PCIe Gen3 x8 and get an errors which compiles succesfully with Q18.1.1

I get this error message:

Error(14996): The Fitter failed to find a legal placement for all periphery components

   Error(14986): After placing as many components as possible, the following errors remain:

      Error(13081): The Fitter cannot route to 1 clock core fanout

         Error(16234): No legal location could be found out of 31 considered location(s). Reasons why each location could not be used are summarized below:

            Error(177003): Fitter encountered congestion in the clock network while routing from source auto-promoted clock driver to the clock core fanout

            Error(14903): The following regions are not compatible given the current clock driver placement (30 locations affected)

      Error(13081): The Fitter cannot route to 1 clock core fanout

         Error(16234): No legal location could be found out of 31 considered location(s). Reasons why each location could not be used are summarized below:  

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3 Replies
BoonT_Intel
Moderator
278 Views

Hi Maybe you can remove all user constraint from the QSF and let quartus auto fit the design.

User1573261788318367
278 Views

I have seen this error before when choosing invalid pin placement, direction, and/or I/O standard for the PCIe pins.

CLeon14
Beginner
278 Views

Thank you. I am able to get it fix after remove some location assignment.

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