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PVanL
Novice
66 Views

PCIE example issues

I am using the PCIE Example as described in UG-20234. As i want to connect another application behind the hard-IP EP, i am modifying the testbench and APPS to allow transfers >4 bytes, which is how the example is written. The idea is: i verify in simulation, before mapping it onto the FPGA, debugging on a mapped design is way more time consuming then in simulation.

It is configured for 64 bit/250 Mhz / Atlanta interface between HardIP and APPS.

I managed to send 8 bytes to APPS, which sends those 8 bytes to memory, and returns them again. I then add 1 to each byte, to be sure i do not mix up with the sent information. The comparator at testbench detects the differences, and goes on playing (in the example it stops when send != receive. ) I adapted the header for the CmplD TLP from

|          77 RX |      MWr      | 0004    | 60000001_0000000F_00000001_00010000  |

|          77 RX |      MRd (00) | 0004    | 20000001_0000000F_00000001_00010000  |

|          77 TX |     CplD (00) | 0004    | 4A000001_01080004_00000000           |

|          77 RX |      MWr      | 0004    | 60000001_0000000F_00000001_00010000  |

|          77 RX |      MRd (00) | 0004    | 20000001_0000000F_00000001_00010000  |

|          77 TX |     CplD (00) | 0004    | 4A000001_01080004_00000000           |

(for 8 byte) to

|          77 RX |      MWr      | 0008    | 60000002_000000FF_00000001_00010000  |

|          77 RX |      MRd (00) | 0008    | 20000002_000000FF_00000001_00010000  |

|          77 TX |     CplD (00) | 0008    | 4A000002_01080008_00000000           |

 

The Header for 8 byte has the following TLP fields, which are to my knowledge correct:

For MWr:

DW0         60000002: length = 2, Fmt = 2’b11”, Type = 5’b00000 => strange: Fmt should be 2’b10 for MWr!!!??? (this is made by INTEL IP)

DW1         000000FF:  1stBE = F, Last_BE = F, Tag = 0, ReqID = 0 (Made by Intel IP)

DW2         00000001: why is DW1[0] = R=1, this should be 0  !!!!???? Address = 0 (Made by Intel IP) In reality it is 0000_0000 !!! (bug)

DW3         00010000 = ???? (should be data???!!!). But the data arrives correctly in the memory (Made by Intel IP) In reality it is data[31:0]

DW4: (not depicted in this table) data[63:32] works correctly

 

For Mrd:

DW0         20000002: Length = 2, Type = 5’b0000, Fmt = 2’b01 => strange: Fmt should be 2’b00 for Mrd (Made by Intel IP)

DW1         000000FF: :  1stBE = F, Last_BE = F, Tag = 0, ReqID = 0 (Made by Intel IP)

DW2:        00000000: why is DW1[0] = R=1, this should be 0  !!!!???? Address = 0 (Made by Intel IP)

 

For CplD

DW0         4A000002: Length = 2, Type = 5’b01010 (correct), Fmt = 2’b10 (correct) (Made by me)

DW1         000000FF: :  1stBE = F, Last_BE = F, Tag = 0, ReqID = 0 (Made by me)

DW2:        00000001: why is DW1[0] = R=1, this should be 0  !!!!???? Address = 0 (Made by Intel IP), in reality it is 0000_0000

DW3         data[31:0]

DW4         data[63:32]

For some reason this does not work:

The DUT PCIE hard IP does not produce nice continuous tx0..tx3 signals: they are interrupted with ‘x’ s.

In the testbench, the signal is routed via rx0..rx3 to altpcietb_bfm_rpvar_64b_x8_pipen1b. The output of rpvar: rx_data0 0000000000000000 rx_desc0 044a000002010800080000000078561011 rx_be f4 rx_dv 0 rx_dfr 0 rx_ack 0 rx_abort 0 rx_retry 0 rx_mask 0 rx_ws 0  Where the last 8 bytes are correct = data[31:0] sent!

My questions:

Why does this not work? Options:

  1. the header for MRd is not correct, but this is generated by INTEL testbench?
  2. The header for ClpD is not correct (this is generated by my modifications)?
  3. The HardIP in DUT has a configuration that only allows 4 bytes?
  4. The rpvar mimic can only handle 4 bytes?
  5. The rpvar needs a modification of parameters?
  6. And how do I make it working?

Thanks in advance! Pieter

0 Kudos
6 Replies
52 Views

Hi,


Could you share both the settings/.qsys file you used to create the example design and the files after modification?


Thanks.

Best regards,

KhaiY


PVanL
Novice
48 Views

Dear KhaiChein_Y, thanks for reaching out.

I assume the name of the zipfiles speak for its content.

Main changes:

  1. splitted altpcietb_bv_rp_gen2_x8 into two files: altpcie_bfm_rpvar and  altpcietb_bv_rp_gen2_x8_ex_rpvar, to make the editing of the last more easy
  2. added many $fdisplay statements to more easily track bitstreams (i always get lost in the wave screen)
  3. changed a lot in tlp_parser to generate headers for 8 byte CplD. The result of that can e.g. be seen in outparsout.txt
  4. added 8 byte wide write to and read from memory (interconnect_low and ~high, and mem_low and ~high) in pcie_ed
  5. changed a bit in downstream_driver to generate 8 bytes.
  6. in pcie_ed, line 546 and 566, 1 is added to each read byte
  7. In the downstream_drive file, line 465, Length = 4, as written by INTEL. If you run the testbench, it fails of course because of the adding of 1 to each byte. But downstream_drive is modifies such, that it does not stop, it just reports a difference.
  8. Change this line 465 to 8, and the tb sends 8 byte, the apps writes it to MEM in pcie_ed, read it back, adapts the TLP headerfiles, of which you can see the result in pcie_ed_tx.txt, and eventually sends seemingly correct data to the HardIP.
  9. At receipt in TB, in rpvar, rx_data remains zero, but rx_desc0 has some recognizable values. Also, there are 'x' in the serial wires tx0..3 from the DUT, to the rx0...3 of rpvar. This suggests that the HardIP of PCIE is not controlled correct by TLP headers? configuration setting?
  10. I hope this clarifies, please do not hesitate to ask clarification if needed.

Regards ,Pieter

PVanL
Novice
21 Views

Dear KhaiChein_Y

 

I did not receive a reaction from you yet. Please respond.

Regards, pieter

17 Views

Hi pieter,


I am still working on this. Please allow me some time.


Best regards,

KhaiY


PVanL
Novice
15 Views

Hi KhaiY,

Glad to hear you are still on it....

Of course, i understand, it is a F**ng difficult testbench / apps / bfm. But i was triggered by INTEL if the answer provided was sufficient to close the call. (i thought with all those smart AI of today, the bot would have seen there is just a question (yours) and an answer (mine).....)

 

Regards, Pieter

PVanL
Novice
2 Views

Dear KhaiChein_Y

Can you give me an update where you stand, or how i can help you, if at all, with getting the simulation running? regards, Pieter (....i am trying not to sound impatient.....)