The documentation for the stratix IV is somewhat confusing on this matter. It says:"Offset cancellation logic requires a separate clock. In PCIe mode, you must connect the clock input to the fixedclk port provided by the ALTGX MegaWizard Plug-In Manager. The frequency of this clock input must be 125 MHz. For all other functional modes, connect the clock input to the reconfig_clk port provided by the ALTGX MegaWizard Plug-In Manager. The frequency of the clock connected to the reconfig_clk port must be within the range of 37.5 to 50 MHz. Figure 1–46 shows the interface of the offset cancellation control logic (ALTGX_RECONFIG instance) and the ALTGX instance." The ALTGX instance has a "fixedclk" input and a "reconfig_clk" input, and the ALTGX_RECONFIG instance has a "reconfig_clk" input. The ALTGX fixedclk input should definitely be 125 MHz, but what should the reconfig_clk inputs be? It sounds like it should be connected to the same 125 MHz fixedclk input on the ALTGX instance, but it says numerous times that fMax for reconfig_clk is 50 MHz. Can anyone clarify?
While waiting for a better answer, here is my experience. I have not used the PCIe mode, but did use other modes that require the reconfig_clk. the reconfig_clk must be between 37.5 and 50 MHz. The doc also says that the reconfig_clk must come from an input pin. However, there is an app note (forgot which) that shows you how to use a pll for that - in case you do not have a separate 37.5 to 50 MHz clock coming in.Knowing what the reconfig block does, I don't think they would require the reconfig_clk to be different for PCIe. Here is the link to using a pll for reconfig_clk: http://www.altera.com/support/kdb/solutions/rd12172009_309.html
For PCIe core, fixedclk must be 125MHz which is used to control transceiver data path of Offset Cancellation process. There is no other frequency allows for fixedclk. Whereas, reconfig_clk can be from 37.5 to 50MHz that is used to control the reconfig block controller.