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Is the Slot Number information provided in the PCIe header (AXI Streaming IP, Document ID: 790711) the same as the Physical Slot Number of Slot Capabilities Register [31:19] defined in the PCIe Base Specification?
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Hi,
Both are not define the same thing, Slot Number in the PCIe header and the Physical Slot Number in the Slot Capabilities Register serve different purposes within the PCIe architecture. The former is used for transaction routing and identification, while the latter is used for system management and configuration.
Regards,
Wincent
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"The former is used for transaction routing and identification," which can be achieved by Bus and Device numbers or using the Address mapping to BAR. How does this field differ from them? Could you provide more details?
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Hi ,
Detail about the slot number, you may refer to the user guide under section 6.3.3
let me know if you need further clarification.
Regards,
Wincent_Altera
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Hi,
I wish to follow up with you about this thread. Do you have any further questions on this matter ?
Regards,
Wincent_Altera
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Hi,
As we do not receive any response from you on previous question/reply/answer that we provided. Please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of desire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.
Regards,
Wincent_Altera
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Hi Wincent,
Thanks for your response.
How will the mapping of these end-points based on slot number be done? Is it handled by the main system in the Hierarchy (Root Port) or by the user through user-defined interfaces?
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Hi Muneet,
For example if you are using D-state you write the slot number accordingly to the bit
https://www.intel.com/content/www/us/en/docs/programmable/790711/24-3-1/d-state-sts.html
You may refer other register name in section 7 as well.
Regards,
Wincent

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