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Altera_Forum
Honored Contributor I
766 Views

PCIe Avalon-MM 32-bit reads

Is the PCIe Avalon-MM implementation limited to 64 bit transfers? I'm not seeing the PCIe IP use the Avalon byteenables correctly to size the transfer. Is the IP limited to only supporting 64-bit accesses?

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Altera_Forum
Honored Contributor I
26 Views

Did you ever figure this out, I am wondering this myself. I am having a problem because it accesses a register that triggers an event on a read.