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PCIe Avalon-MM DMA MSIs assignment of AN829

Ursa
Beginner
405 Views

Dear All,

Before starting our own project, I am trying to program the Windows KMDF driver firstly on Arria 10 GX dev board based on the AN829 example.

In the doc of AN829, I found the "Number of MSI messages requested" is 4, however I don't know the purpose of each MSI, eg. which one is for reading, writing or something else? Can anyone tell me the detailed descriptions of MSIs of AN829 example? Thanks a lot. I need to distinguish the messages from each other in ISR.

By the way, how can I assign an MSI ID for different interrupt purpose? It seems that I can only set the number of MSI messages like this.

Ursa_0-1608695815073.jpeg

Best regards,

Ursa

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3 Replies
Rahul_S_Intel1
Employee
383 Views

Hi ,

Kindly find the details of the MSI interrupt on page no: 97 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

for detailed description 

Ursa
Beginner
342 Views

@Rahul_S_Intel1 Hi Rahul,

Thanks for guiding. Looks like I need to access the register 0x3060(PCI Express to Avalon-MM Interrupt Status Register for Endpoints) to distinguish the signals, but I don't know how to access Avalon-MM Control and Status Register Address Spaces from Windows side. Should I expose these spaces through a BAR? Any suggestions? Thank you very much.

Ursa
Beginner
341 Views

@Rahul_S_Intel1 Hi Rahul,

Thanks for guiding. Looks like I need to access the register 0x3060(PCI Express to Avalon-MM Interrupt Status Register for Endpoints) to distinguish the MSI signals. But I don't know how to access the Avalon-MM Control and Status Register Address Spaces from Windows side. Should I expose these address spaces through a BAR? Any suggestions? Thank you very much.

Regards,

Ursa

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