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PCIe Avalon-MM-to PCI Express Address Translation Table

Altera_Forum
Honored Contributor II
1,351 Views

Hi 

 

I am using Altera PCIe compiler with dynamic translation table with 8 MB per page. I connect BAR 0 to CRA with base address of 0x0000_0000.  

 

I write the physical address of host system 0x0022_0000 into PCIe CRA address at 0x1000 via BAR 0, the data read back is 0x0000_0000. 

When I write the physical address of host system 0x0088_0000 into PCIe CRA 0x1008, the data read back is 0x0080_0000.  

 

May I know why? Can’t be any address of physical address? How does the translation table partition the physical memory?  

Is the physical memory is divided equally according the page size if use the altera PCIe? 

 

Thanks
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3 Replies
Altera_Forum
Honored Contributor II
189 Views

I am having almost exactly the same problem.  

 

Did you resolve this and, if so, how?  

 

Thanks
Altera_Forum
Honored Contributor II
189 Views

Yes, i have solved it. Basically, you just have to refer to Avalon-MM-to-PCI Express Address Translation. It answers all the questions asked.

Altera_Forum
Honored Contributor II
189 Views

OK we got it. We made a mess of the writing. It works now.  

 

BAR + CRA BASE + REG OFFSET worked.
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