I am attempting to port a PCIe Avalon-MM w/ DMA flavor's 'APP' and 'DMA' layer to layer on top of an Avalon-ST flavor of the PCIe Hard IP core. Looking at the design, there seems to be a particular interface that differs between the 2 flavors -- namely the MSI. Are interface signals listed below somehow implicitly wired internally to the PCIe Hard-IP, or are they not used?
output logic [81:0] AvMsiIntfc_o,
output logic [15:0] AvMsixIntfc_o,
output logic [15:0] Msi_control_o,
Looking at it in RTL viewer, it appears to not route anywhere downstream. I also seem to believe completions are in band and are handled at a packet level and thus be handled by the read/write data mover logic.
On another note, if there is a better method to leveraging the DMA IP to a Gen2 x2 and lower PCIe version, I am open to recommendation to do so...
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you