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Altera_Forum
Honored Contributor I
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PCIe Compiler 10.1 Soft Core can't meet timing?

Good evening, 

 

I'm trying to use the PCIe Soft IP Core in a Cyclone IV E design, but I can't seem to get the chaining_dma example project to meet timing. I'm using a PX1011B PHY (setting the core to use a custom x1 PHY with an 8-bit SDR + TxClk). I'm trying to build for EP4CE55F23I8L with a 62.5MHz application clock. 

 

Essentially what I'm doing is opening Quartus 2 (web edition), bringing up the MegaWizard for the PCIe compiler, setting it up as mentioned above, leaving everything else at defaults. Then I open the chaining_dma example project, set up the device, setting up "Perform register retiming" "Perform register duplication" and "Perform physical synthesis for combinatorial logic" as per the user guide for the core. I've also set the Analysis and Synthesis optimization level to "Speed". 

 

I then set up a connection group for the PHY connections (*ext, pipe* and refclk), constrain them to a single IO block (3 in my case) and set the block to SSTL-2 class I logic levels. I don't adjust or constrain anything else. I have tried locking the refclk to a CLK input in that IO block as well as locking the txclk to a PLL output, but that didn't help. 

 

I can't get the Cyclone IV E I8L or I7 to meet timing with either 125MHz or 62.5MHz application clocks. I also tried the Cyclone III I7 devices (EP3C40F484I7) with both 125MHz and 62.5MHz application clocks but they won't meet timing either. I tried Cyclone III because the user guide specifically lists the 6,7,8 speed grades of that device. 

 

I've tried Quartus II web edition for Linux and Windows, and a friend tried it with the subscription edition on his Win64 box with the same results. He is more experienced than I am and has mentioned that the timing problem is on the output of a dcfifo, which "is bad". :-) 

 

I found a few app notes and some forum posts but nothing stood out as that eureka item that I was missing. It's clear to me that earlier versions of the soft IP core work, and I can't imagine the core being at fault, but I am running out of ideas. 

 

One of the app notes suggested opening the pin planner and importing the MegaFunction's .ppf file, but that gave the exact same results. 

 

Has anyone been able to get this core to work with Quartus II 10.1 web edition? Is there something really dumb I'm overlooking?
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Altera_Forum
Honored Contributor I
34 Views

With the help of some more experienced friends it appears that the trouble was due to a few things: 

 

1) the "Placement Effort Multiplier" in the Advanced Settings of the Fitter is now set to 4.0 (default value was 1.0). 

2) the Optimization Technique in the Analysis and Synthesis Settings is now set to "Speed" 

 

With these two changes I did NOT need to set anything different under the physical synthesis settings (the user guide suggests setting "Perform register retiming", "Perform register duplication" and "Perform physical synthesis for combinatorial logic." Setting these things does not allow the core to meet timing; I had to set the two things listed above in order to meet timing. 

 

One thing that I noticed did NOT matter was the PHY interface clock speed; 250MHz IO does not appear to be a problem with the I8L part.
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