Re: PCIe Control Register Access - QSYS - Nios

Altera_Forum · ‎09-02-2011

I'm using Qsys in order to interface my Nios application to an external microprocessor via PCIe Interface.

After Nios do some operations I need to generate a IRQ toward PCIe in order to advice the external processor that data are ready, etc.

In order to do that in my Qsys system I've interconnected Nios_Data_bus with PCIE control register access and also the Nios Interrupt Sender to PCIE CRA Receiver.

I've 2 different problems in Nios II environment (consider that I'm quite new in software writing, so maybe some are mistakes).

1- First I expected in NIOS system.h some# define register to access to PCIe IRQ Enable and IRQ Status, whereas I found only:

# define __ALTERA_PCIE_HARD_IP

and also

/*

* PCIe configuration

*

*/

# define ALT_MODULE_CLASS_PCIe altera_pcie_hard_ip

# define PCIE_BASE 0x8000

# define PCIE_IRQ 4

# define PCIE_IRQ_INTERRUPT_CONTROLLER_ID 0

# define PCIE_NAME "/dev/PCIe"

# define PCIE_SPAN 16384

# define PCIE_TYPE "altera_pcie_hard_ip"

In reality PCIE_BASE is exactly the mapping of PCIe CRA in my NIOS memory, so that's ok.

Other than that I've no clue on how use these informations..

In order to generate a IRQ toward PCIe, I've understand that I've to enable interrupt RXm_IRQ writing at CRA_BASE_ADD + 0x50 and that then I'll set the interested IRQ writing at CRA_BASE_ADD + 0x50.

Is that all right?

I think that it is very strange that in System.h I do not have any reference to the CRA internal registers as with all others perypheral I've used.

2-

To overcome to this "problem" I've generate an external file .c

# define AVALON_MM_TO_PCIE_IRQ_ENABLE (0x50U)

# define AVALON_MM_TO_PCIE_IRQ_STATUS (0x40U)

void pcie_irq_ena(alt_u32 pcie_csr_base_addr, alt_u16 irq_mask)

{

IOWR_32DIRECT(pcie_csr_base_addr, AVALON_MM_TO_PCIE_IRQ_ENABLE, irq_mask);

}

/* GENERATE THE IRQ */

void pcie_irq_gen(alt_u32 pcie_csr_base_addr, alt_u16 irq_mask)

{

IOWR_32DIRECT(pcie_csr_base_addr, AVALON_MM_TO_PCIE_IRQ_STATUS, irq_mask);

}

/* RESET IRQ */

void pcie_irq_clear(alt_u32 pcie_csr_base_addr, alt_u16 irq_mask)

{

IOWR_32DIRECT(pcie_csr_base_addr, AVALON_MM_TO_PCIE_IRQ_STATUS, ~irq_mask);

}

I think that I've missed something..

Altera_Forum · ‎09-03-2011

The reason why system.h doesn't generate anything useful to create the interrupt is because the interrupt isn't destined to be serviced by the Nios II core. The system.h file revolves around Nios II being the host but in your case the host is whatever processor is sitting on the other side of the PCIe switch.

If you are looking to create an include file to be used by something other than Nios II, I would take a look at this document: http://www.altera.com/literature/hb/nios2/n2sw_nii52018.pdf Also there is a command line tool that will allow you to generate a system.h file for any master in your system. You can run 'sopc-create-header-files --help' to find out more details about that.

Altera_Forum · ‎09-03-2011

That's very clear and quite obvious.

I thought that having attached Nios data bus with PCIe CRA something more should have been referenced, but you're right in my case the host is the other micro on the other side of PCIe.

Thank you and have a nice week end

Altera_Forum · ‎03-26-2013

Darkwave, have you successfully sent a TLP via the CRA Slave ?

If so, did you have any problems with the directions , registers or bit difinitions defined in the

users guide for "Sending a TLP"