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5950 Discussions

PCIe DMA based Linux Driver

Altera_Forum
Honored Contributor II
886 Views

Hi, 

 

I am developing one sample PCIe based X86 Linux Driver to read/write data from/to SD Card which is connected in Altera Cycleon V FPGA Board. 

 

I am able to successfully read/write data in onchip memory, PIO test register as well as our custom SDHC Host controller registers from my PCIe driver without any issue. 

 

Now, I am planning to read/write data from/to SD Card using Chaining DMA Concept. We have DMA Controller as in built into our SDHC Host Controller which is used to access SD Card connected on FPGA board.  

 

Do I need to connect our DMA Read Master and Write Master Control Port to any of BAR region from FPGA design to access that DMA Interface directly from Linux PCIe Driver? or Do I need to connect to DMA Read and Write Master Control Port to any Internal Memory of FPGA Board to access it from Linux PCIe Driver? 

 

Please find attached image of our FPGA design from more information. 

 

Please let me know if anyone has idea about it. 

 

Regards, 

Ritesh Prajapati
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
104 Views

The seems to depend on whether the control ports are avalon masters or avalon slaves.

Altera_Forum
Honored Contributor II
104 Views

Hi dsl, 

 

Thanks for your reply. 

 

I am working on FPGA design and Ritesh is developing PCIe driver from Host Side.SDHC IP Core has both Avalon Slave and Avalon Master Interface.Avalon Slave interface is used to configure register of SDHC IP Core(including DMA registers) and Avalon Master Interface is used to transfer data between SDHC IP Core and other Avalon Slave Interface.Normally we connect SDHC IP Core Avalon Master Interface to Avalon Slave Interface of Memory Controller.However in this design,we don't have any external memory.(Onchip Memory is used for testing purpose only).In actual design there will be only two IP Core,one for PCIe and other for SD Card.In existing design,I have connected SDHC Avalon Master Port to Txs port of the PCIe IP Core (took reference from PCIe User Guide example). Please see the attached Qsys design connection.Now we don't know how to access Txs port from the Host Side PCIe driver. 

 

Would you please provide your suggestions. 

 

Thanks, 

 

Krupesh
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