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Altera_Forum
Honored Contributor I
3,646 Views

PCIe Driver

Hi everybody, 

 

I`m new on this forum and in the usage of Altera product, then be patients please. I`m not able to find the answer to my questions. I want read and write from my FPGA (Stratix V) to the Host PC RAM, using PCIe bus, without involve the CPU. In the specific, FPGA writes in RAM and when the data transfer is finished, FPGA sends an interrupt to the CPU. When CPU receives the interrupt from the FPGA, reads data from PC RAM. I`m able to realize the FPGA side but not the PC driver. My questions are: 

 

Is there some driver, API or library to do that? where can I find them? 

If not, how can I realize the PC driver? is there a good guide that explain how realize driver? 

 

Thanks you very much 

 

Federico
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10 Replies
Altera_Forum
Honored Contributor I
366 Views

The link below has some PCIe example designs and also a Jungo driver (altpcie_demo.zip) used at the host side. 

https://www.altera.com/support/support-resources/software/download/refdesigns/ip/interface/dnl-pciex... 

 

Application note AN456 has more information on how to run the software driver. 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an456.pdf
Altera_Forum
Honored Contributor I
366 Views

Thank you very much skbeh :)

Altera_Forum
Honored Contributor I
366 Views

Linux or windows host? 

It is all much easier on Linux....
Altera_Forum
Honored Contributor I
366 Views

 

--- Quote Start ---  

Linux or windows host? 

It is all much easier on Linux.... 

--- Quote End ---  

 

 

Hi, dsl thanks for your reply. 

 

I`m looking for Windows and Linux. I have found some driver developed with Jungo connectivity for Windows, but there is not the .h files.
Altera_Forum
Honored Contributor I
366 Views

You can get the linux driver and source code at http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs 

Scroll down to the "Software" section of this link and download the driver & software source code.
Altera_Forum
Honored Contributor I
366 Views

The copy of the linux jungo driver that is referenced from some other Altera docs is very old and broken beyond belief. 

It won't compile for any recent linux and internally does a load of things that just aren't allowed - so it isn't a matter of fixing up the compilation errors. 

I doubt (not looked) that the version referenced by the wiki is any better. 

 

Accessing the fpga resources directly from userspace just requires a simple driver that uses vm_iomap_memory(). 

Allocate dma memory with dma_zalloc_coherent() and map into usespace with remap_pfn_range(). 

You might need 3.13 or later.
Altera_Forum
Honored Contributor I
366 Views

Thanks for yours replies. I have found some source files for Linux on the Altera website (I do not remember where) but I have not tried yet. I have also found the Jungo windows driver from an Altera example but I do not know how I can use them because there is not any documentation. For now I`m still working on the FPGA configuration, I`m going to be able to give you more details when I start to work to the PC program.

Altera_Forum
Honored Contributor I
366 Views

Hello, now I`m work on the PC driver, I have found some examples on the wiki Altera that use the Jungo driver but they do not include the header files. I have downloaded the Jungo trial program. It generates the drivers and the header files for my PC program. Is there some examples (source code) for better understand how I must use the header files? Or is there a better solution instead of using Jungo?

Altera_Forum
Honored Contributor I
366 Views

Hello, I have a problem with the Jungo drivers that I`m trying to develope. I downloaded an example from Alterawiki, in the specific, the link is: 

 

http://www.alterawiki.com/wiki/reference_design_-_gen3_x8_avalon-st_256-bit_-_stratix_v 

 

And it works great. I have substituted the Jungo driver of this examples with the driver that I have created with Jungo WinDriver. When I launch the .exe that I have generate using my compiler I can see the device, read and write the BAR registers but I cannot read and write using DMA. 

 

My program return an exception when initialize the DMA device in DMADevicePrepare function. The function that return an exception is: 

 

/* Try to check the address translation path through */ 

/* (0x1000 is the offset for the translation register) */ 

WDC_WriteAddr32(hDev, AD_PCI_BAR2, 0x1000, 0xFFFFFFFC); 

/* Read the path through mask */ 

u32A2PMask = ALT_ReadReg32(hDev, AD_PCI_BAR2, 0x1000); 

 

 

I have solved my problem on Windows using the Riffa interface. Now I`m working on Linux I have found this example: 

 

 

http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_strati... 

 

 

I have downloaded the Linux Driver and I would like use these drivers to write a linux application. I'm looking for a framework for communicating data from a host CPU to a STRATIX V via a PCI Express bus with bindings for C/C++ that supports Linux. Someone knows if are there some documentation or the API for these driver? Or are there some equivalent example for the StratixV with the working linux drivers (with documentation and API)?
Altera_Forum
Honored Contributor I
366 Views

Hi everybody, 

 

I have solved my problem on Windows using the Riffa interface. Now I`m working on Linux I have found this example: 

 

http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_strati... 

 

I have downloaded the Linux Driver and I would like use these drivers to write a linux application. I'm looking for a framework for communicating data from a host CPU to a STRATIX V via a PCI Express bus with bindings for C/C++ that supports Linux. My problem is that I can not find any documentation or the API to use these drivers. Someone knows if are there some documentation or the API for these driver? Or are there some equivalent example for the StratixV with the working linux drivers (with documentation and API)?
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