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Altera_Forum
Honored Contributor I
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PCIe Example Design Simulation Failing

Hi everyone, 

 

I am getting stuck simulating the Avalon-MM Hard IP for PCIe for an Arria V GX. I am using the Getting Started with the Avalon-MM Arria V Hard IP for PCI Express part of the User Guide. When I try to simulate(ncsim) it stalls always in the same state and the simulation fails. 

 

# 464 ns Completed initial configuration of Root Port.# INFO: 2657 ns EP LTSSM State: DETECT.ACTIVE# INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE# INFO: 6049 ns EP LTSSM State: POLLING.ACTIVE# INFO: 6909 ns RP LTSSM State: POLLING.ACTIVE# INFO: 9037 ns RP LTSSM State: POLLING.CONFIG# INFO: 9441 ns EP LTSSM State: POLLING.CONFIG# INFO: 10657 ns EP LTSSM State: CONFIG.LINKWIDTH.START# INFO: 10829 ns RP LTSSM State: CONFIG.LINKWIDTH.START# INFO: 11713 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT# INFO: 12253 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT# INFO: 12573 ns RP LTSSM State: CONFIG.LANENUM.WAIT# INFO: 13505 ns EP LTSSM State: CONFIG.LANENUM.WAIT# INFO: 13825 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT# INFO: 13853 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT# INFO: 14173 ns RP LTSSM State: CONFIG.COMPLETE# INFO: 14721 ns EP LTSSM State: CONFIG.COMPLETE# INFO: 16001 ns EP LTSSM State: CONFIG.IDLE# INFO: 16093 ns RP LTSSM State: CONFIG.IDLE# INFO: 16285 ns RP LTSSM State: L0# INFO: 16545 ns EP LTSSM State: L0 

 

After this the simulation stops and fails. 

 

Any ideas? 

 

Thanks.
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