I've built a design around a Stratix V and the Avalon-ST Hard IP Core. The device is designed for Gen3x8 which is working fine.I now want to connect the design to a laptop via a Gen1x1 ExpressCard Slot. I have a OneStop Systems express card cable adapter (OSS-ECA-x4 and OSS-PCIe-HIB2-EC-x4). On one laptop, the device correctly enumerates at Gen1x1 and works as expected. However on a second laptop, the core fails to properly enumerate - sometimes doesn't select the correct number of lanes and so fails to appear at all. Other times it does enumerate, but only very late on after windows has started up. Looking at the configuration registers, on most attempts to boot there are fatal errors detected (read the configuration space and it indicates errors). Only very occasionally does it successfully enumerate. I compiled a gen1x1 variant of the core, which does enumerate correctly, but (a) it means I have to have two versions of the firmware to keep up to date which I would rather not do, and (b) I will have to do a lot of debugging of my application layer again to make sure it works with the slower clock frequency (there are clock crossing considerations) and narrower bus (64bit rather than 256bit), so really would rather get the Gen3x8 properly enumerating on Gen1x1. As far as I can tell the laptop that is misbehaving being quite modern supports Rev2.0 of ExpressCard which basically says that it is allowed to run the PCIe lane at Gen2. Sure enough the north bridge chipset of it also supports Gen2. The old laptop which is working however predates Rev2.0 of ExpressCard, so is limited to Gen1. I have a sneaking suspicion that the Stratix V is trying to jump up to Gen2 and failing. As there are redrivers in the cable that only support Gen1 any attempt to run faster will simply result in garbled signals - in fact looking on a oscilloscope at the traces they do seem to double in speed. So the question is, is there a way to force the Stratix V Avalon-ST Hard IP core to not go above Gen1 using something like a dip switch setting? - i.e. I don't want it to be a synthesis parameter, I want to be able to flick a switch at have it be limited to Gen1.
If the pcie core is configured to gen2 and if the laptop also supports gen2, the link will automatically train to gen2, there is no hardware setting such as dip switch to prevent it train above gen2, you still need to regenerate the pcie core to gen1 if want it to operate at gen1.If the redrivers in the cable only support Gen1, the link will only trains to gen1.
That's what I would assume, except it fails to enumerate correctly on this particular laptop with the Gen3x8 configuration, but does enumerate with a Gen1x1 core (though the clock frequency and data width changes of the core mean that I will have to do a lot more testing to get my application layer for that one working). It's possible I suppose that it is an issue with the fact that there are 8 lanes, of which 4 aren't connected on the OSS board (they will be floating inputs) and 3 aren't used.I see that there is a Hard IP Reconfiguration Interface which looks like it should be possible to reconfigure the compiled core. But there is no register listing saying what can be changed.
If the core is Gen3x8, the endpoint card should be no problem connect with x1 lane ExpressCard Slot, the rest of 7 floating and unused channels won't cause link-up issue, during enumeration the rootport and endpoint will negotiate to the lowest and common lane/s, which is x1.
The hard IP reconfiguration interface is use to dynamically modify the value of configuration registers that are read-only at run time, such as device ID and vendor ID. But even this also very rare users use it.The speed and lanes width were already setup and pre-defined during enumeration and handshaking process between rootport and endpoint. I'm not sure if the reconfiguration interface can be used to modify the speed and lane width.
The dynamic reconfiguration to change internal register is quite tricky, I guess no one want to use this method, people would rather compile 2 versions of core with different speed and lanes.