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Altera_Forum
Honored Contributor I
1,112 Views

PCIe Gen3 on DE5-net/Stratix V board

Hi All,  

 

I've been trying to create a simple design using the Stratix V PCIe 3.0 x8 core with an Avalon-ST interface. I can compile my design, and load it onto the FPGA, but link training fails to achieve Gen3 Speeds. 

 

For instance, this is the output of signal tap when I capture the LTSSMSTATE and CURRENTSPEED signals.  

https://www.alteraforum.com/forum/attachment.php?attachmentid=8668 As you can see, the core reaches Gen3 speeds, and also reaches L0, but soon drops back down into Gen2. I was creating a Gen2 Core earlier, and found a similar problem when my analog pin settings were incorrect, so I would assume that my analog pin settings are incorrect. Currently, each RX pair has the settings: 

 

set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_in[0] 

set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to pcie_rx_in[0] 

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_rx_in[0] 

set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to pcie_rx_in[0] 

 

 

set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "pcie_rx_in[0](n)" 

set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "pcie_rx_in[0](n)" 

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "pcie_rx_in[0](n)" 

set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "pcie_rx_in[0](n)" 

 

 

set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to pcie_rx_in[0] 

set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to "pcie_rx_in[0](n)" 

set_instance_assignment -name XCVR_RX_SD_OFF 5 -to pcie_rx_in[0] 

set_instance_assignment -name XCVR_RX_SD_OFF 5 -to "pcie_rx_in[0](n)" 

set_instance_assignment -name XCVR_RX_SD_ON 1 -to pcie_rx_in[0] 

set_instance_assignment -name XCVR_RX_SD_ON 1 -to "pcie_rx_in[0](n)" 

set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to pcie_rx_in[0] 

set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to "pcie_rx_in[0](n)" 

set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to pcie_rx_in[0] 

set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to "pcie_rx_in[0](n)" 

 

and each TX pair has the settings: 

 

set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_out[0] 

set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to pcie_tx_out[0] 

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_tx_out[0] 

set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to pcie_tx_out[0] 

 

 

set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to "pcie_tx_out[0](n)" 

set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL PCIE_GEN3 -to "pcie_tx_out[0](n)" 

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to "pcie_tx_out[0](n)" 

set_instance_assignment -name XCVR_VCCA_VOLTAGE 3_0V -to "pcie_tx_out[0](n)" 

 

 

 

So my question is, has anyone gotten an Gen3 design to operate at Gen3 speeds, and would they be willing to share their settings? It's a true shame that altera doesn't provide an example design for Gen3 with an associated QSF file for reference. 

 

Thanks in advance,
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3 Replies
Altera_Forum
Honored Contributor I
61 Views

Hi there, 

 

Could you share your BIOS settings and motherboard model with us ? Based on our experience, it would be the best to fix the setting of that particular PCIe bus to "Gen3" instead of "Auto".  

 

In case you haven't had chance to search Altera's website, you could also refer to http://www.altera.com/literature/ug/ug_avmm_256_dma_gen3x8.pdf, despite the difference between Avalon-ST and Avalon-MM interfaces. 

 

Thanks, 

 

David from Terasic
Altera_Forum
Honored Contributor I
61 Views

Hi David,  

 

Pinning the slot to Gen3 seems to have fixed the problem, thanks! 

 

For reference, my analog settings above match the ones in the example design online.  

 

Mu
Altera_Forum
Honored Contributor I
61 Views

Some additional sharing, for Stratix V PCIe 3.0 x8 core with Avalon-ST interface, make sure to instantiate the Reconfig Driver in the design. Otherwise link downtrain may also occur. 

The requirement to add the Reconfig Driver was mentioned in the Stratix V PCIe Hard IP user guide.
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