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Altera_Forum
Honored Contributor I
767 Views

PCIe Hard IP: MSI race vs. latest DMA write

Hi! 

 

Does someone know the relationship between the latest DMA write, probably updating some memory structure, and the MSI sent autonomously by the hard IP? When can I assert app_msi_req so I don’t overrun the previous write request? 

 

I use the PCIe Hard IP in AST 64 mode on Arria II GX.
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Altera_Forum
Honored Contributor I
43 Views

Okay, found the paragraph about the MSI datapath in the PCIe Compiler User Guide explaining how to use the adapter fifo states for ensuring correct ordering. 

 

Case closed.
Altera_Forum
Honored Contributor I
43 Views

Case reopened. 

 

Well, the proposed workaround for not having Stratix V, to read the fifo state and wait for the write access to pass the fifo, is only half the way. First, it’s a hack on its own. Second, one has to consider the write access as it flows through the various pipeline stages until it eventually hits the Hard IP. 

 

I decided to do it completely different: Create the MSI TLPs on my own, inside the application. This way I don’t have to care about the fifo inside the hard ip, and the pipelining inside the application can be neglected, too. I added an LMI interface to periodically read and update the MSI address and data from addresses 0x054, 0x058 and 0x05C of the PCI configuration space. Now let’s see how that works out. 

 

Does anyone consider that a bad idea?
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