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5923 Discussions

PCIe IP generate support

Moti
Employee
524 Views

Hi,

 

I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, It is important to me that at gen1

the clock rate will be 250MHz with 8bits data.

at IP Compiler for PCI Express datasheet, I found at Table 3-9 that gen1 support it

but in the mega wizard I didn't find the option that can define it

 

I would appreciate help

Thanks,

Moti

 

0 Kudos
1 Solution
Deshi_Intel
Moderator
460 Views

HI Moti,


I presume you are using PCIe Gen 1 preset in NativePHY IP.


By default, it will be 10 bits with 125MHz.


You can disable the Tx serializer and Rx de-serializer setting then it will become 8 bits with 250MHz.


Refer to the attached pic in my previous post.


Thanks.


Regards,

dlim


View solution in original post

7 Replies
Deshi_Intel
Moderator
515 Views

HI Moti,


We have few PCIe IP solution.


Can you help to clarify which IP and which datasheet doc that you are referring to ?

  • First of all, can you let me know which datasheet doc that you are looking at that clarify support for PCIe Gen 1 with 250MHz ? Can you share with me the doc link and its chapter section/page number ?
  • After that, pls clarify which FPGA IP that you initiated to generate PCIe ? Let me know the exact FPGA IP name. For instance, NativePHY IP or some Avalon MM/ST PCIe or DMA IP and etc...


Thanks.


Regards,

dlim


Moti
Employee
507 Views

Thanks for the quick response,

 

link for the data sheet that I found ( page 47 ) : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf

 

the IP that I choose is L-Tile/H-Tile transceiver Native PHY Intel Stratix 10 FPGA IP, if there is other IP that I can Use for these needs please let me know.

 

Thanks,

Moti

Deshi_Intel
Moderator
489 Views

HI Moti,


Thanks for the clarification.


First of all, the datasheet/doc link that you shared was 2014 old Altera doc that's definitely not applicable to newer Stratix 10 FPGA.


For the list of supported PCIe IP in Stratix 10 FPGA, pls use below link instead


I presume you want to use complete PCIe IP and not NativePHY IP with PCIe PIPE mode only, right ?


Thanks.


Regards,

dlim


Moti
Employee
474 Views

Hi,

I do want to use the NativePhy IP with the PCIe PIPE interface, and for that I need in Gen 1 that work at clock rate of 250MHz with 8bits data.

at the Data sheet that you referred to at Table 103 I can see that this IP support 125MHz with 16bits or 250MHz with 8bits (that what I need)

 

But I did not find at the Mega Wizard any option that can I control this, also when I implement that IP I received data of 16bits at 125MHz.

So how can I change/control that to be 250MHz with 8bits ?

 

Thanks

Deshi_Intel
Moderator
460 Views

Refer to the steps in attached pic

Deshi_Intel
Moderator
461 Views

HI Moti,


I presume you are using PCIe Gen 1 preset in NativePHY IP.


By default, it will be 10 bits with 125MHz.


You can disable the Tx serializer and Rx de-serializer setting then it will become 8 bits with 250MHz.


Refer to the attached pic in my previous post.


Thanks.


Regards,

dlim


Moti
Employee
406 Views

Hi dlim,

 

Further to the question on the page

I saw at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_...

Table 99. PIPE Gen3 32 bit PCS Clock Rates p.172

that I can choose, gen 1 will work with clock of 62.5MHz , How can I choose this clock rate and use it for pipe clk ?

 

Thanks,

Moti

 

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