I'm feeling a bit lost trying to generate interrupts on the host PC over PCI Express. I'm using IP Compiler for PCI Express (13.1) on an Arria II GX togenerate an Avalon-MM master for Qsys. I've pored over the documentation, and have found two different ways that look like they'll generate an interrupt on the host (asserting the rxm_irq lines on the interrupt receiver port, and writing to the mailboxes through the CRA). Poking around at the IP there seems to be a third undocumented mechanism when you check "Enable Exporting User MSI Interface".For my application,I've got 7 possible interrupt signals, numbered 1-7. I'd like to interrupt the host PC and notify it that the interrupt has happened. Depending on what caused the interrupt, there are two different mechanisms that may deassert it, with registers in totally different address spaces. This disinclines me from using the Avalon interrupt mechanism, since it requires that you be able to bind the deassertion of the interrupt to a write on a single slave interface (though I don't know the consequences of violating that rule). That leaves CRA mailbox writes and the mysterious "User MSI Interface"export path. Does anyone have any advice on what the differences here are? The best choice for combination of documentation and suitability seems to the the CRA mailbox, but I'm not particularly clear what actually happens on the host side when I write it. Thanks, Rob
Hello,So their are 2 mechanisms im familiar with . The first is by using the Msi and the standard irq ports like nios has. The standard sound like the one you mentioned on the cra. But I usually don't write to the cra and let qsys handle the interrupt. The msi method can support more irqs since the standard one can only handle 16. Their is a tutorial on altera wikis and is called Msi tutorial. To keep it short Msi expects a message format into the port and then sends the irq to the host. The host then reads the mask register in the cra and tells the irq initiator to desassert the irq. I'll look into the ip compiler to see what mechanisms they have. Some other specific ip cores have easier irq mechanics. -Trukng
MSI-X interrupts are (effectively) edge sensitive.So on the leading edge of the internal IRQ line you must generate the correct PCIe master cycle (by a write through the cra) to raise the interrupt. The host ISR will then need to access the device in order to drop the IRQ line (and then maybe check memory for any actions). For our systems I've written a simple bit of logic that implements the MSI-X-table and pending bit array and writes the high address bits to one of the address mapping tables just before doing the write that raises the interrupt itself. Not difficult and I'm a software engineer.