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PCIe-MM-DMA: Read/Write DMA & BAR0/2 mutually exclusive?

Arintel
Beginner
916 Views

Hi All,

I'm using the Intel PCIe-MM-DMA IP core. In my design, I would often need to schedule a Write-DMA to transfer data from the FPGA to the host system memory. However, sometimes, when there's no data available in the FPGA, the Write-DMA transfer is left pending for a long time. During this pending time, it seems that the host system cannot do any other PCIe activity with the FPGA such as Read-DMA or BAR0/BAR2 accesses until the pending Write-DMA transfer is completed.

Is this by design or a bug in the PCIe-MM-DMA IP core? Or is this a limitation of PCIe in general?

Thanks,

Ari

 

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4 Replies
BoonT_Intel
Moderator
893 Views

Hi,

Just want to understand the problem that you are facing is write-DMA left pending for a long time. Or you are unable to perform the other activity before the write-DMA complete.

If the first one, then may I know how long it left pending? I guess maybe this is due to the FC setting.

If the second one, then I think it is expected behaviour. We need to wait for the write-DMA to complete before we can perform other operation.


Arintel
Beginner
290 Views

Hi,

Thank you for your reply.

It's the second case where I'm unable to perform the other activity before the write-DMA complete.

Is this a limitation of PCIe in general? Or is it possible to customize the IP Core's Descriptor Controller (when generated externally) to allow concurrent Read/Write-DMA and BAR0/2 activities?

Thanks,

Ari

BoonT_Intel
Moderator
273 Views

Hi Ari,

To get the read/write DMA simultaneously, I think we need to modify the software at the RP by allocating RP memory for read/write DMA.

As you can see, it is stated in the UG - Software Program for Simultaneous Read and Write DMA section.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-a10-pcie-avm...


BoonT_Intel
Moderator
260 Views

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