PCIe MSI interrupt

[Sudhirkv]

Hi,

We are working on a custom board using the fpga stratix. In this device data communicates using the PCIE protocol. Please find the below  our PCIE FPGA ip core configuration snapshot. In this we tried to interrupt the MSI, it was not received. Could you suggest how to handle the MSI interrupt, please?

Regards,
Nandhakumar

[KhaiChein_Y_Intel]

Hi,

You may refer to Intel FPGA Wiki - Handling PCIe Interrupts

https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044

Thanks

Best regards,

KhaiY

[Sudhirkv]

Hi,

Thanks for your reply.

Below mentioned our procedure we are following to test MSI interrupt, but we didn't get the expected output.

1. Reading Config space register with offset 0x50

                  Offset : 0x50 Value : 25522181(decimal)

                  Here bit[16] set as 1 to enable MSI interrupts

     2. Reading Config space register with offset 0x4

                Offset : 0x4 Value : 1048582(decimal)

                Here bit[10] is disable , bit[1] (Memory space) and bit[2] (Bus Master)  are 1.

When link is down:-

root@localhost:~# cat /proc/interrupts | grep fpga

65:          0          0          0          0          0          0          0          0   PCI-MSI 3670016-edge      fhgw_fpga_drv

When link is up:-

root@localhost:~# cat /proc/interrupts | grep fpga

65:          0          0          0          0          0          0          0          0   PCI-MSI 3670016-edge      fhgw_fpga_drv

Please find the test log in attached file.

[KhaiChein_Y_Intel]

Hi Nandhakumar,

What device and Avalon interface (Avmm or Avst) you are using? Could you explain how do you trigger the MSI in details?

Thanks

Best regards,

KhaiY

[Sudhirkv]

Hi,

We are using AVMM interface.  Following steps are followed to read MSI interrupt.

1. Set MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register. 
2. Set Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to disable legacy interrupt. 
3. Set bit[1] (Memory space) and bit[2] (Bus Master) of Command Register at configuration space offset register 0x4 to enable the ability to  generate MSI message. 

But in our case interrupt is not generate.

When link is down:-

root@localhost:~# cat /proc/interrupts | grep fpga

65:          0          0          0          0          0          0          0          0   PCI-MSI 3670016-edge      fhgw_fpga_drv

When link is up:-

root@localhost:~# cat /proc/interrupts | grep fpga

65:          0          0          0          0          0          0          0          0   PCI-MSI 3670016-edge      fhgw_fpga_drv

For your reference our PCIE IP configuration snapshot in below. Please check if there is any configuration missing from our PCIE IP.

Regards,

Nandhakumar

[KhaiChein_Y_Intel]

Hi

I am still working on this. Please allow me some time.

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi Nandhakumar,

From the End point, if the Interrupt Enable Register at address 0x50 in CRA, bit15:0 (Control by Host) and RxmIrq_i [15:0] value are set to 1, you should be able to see the MSI request signal. If the MSI request signal is high but not observed in the host, you may consider to use protocol analyzer to check if the host not recognize the MSI request or the end point does not actually send the MSI request.  

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY