FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6421 Discussions

PCIe Memory Read completion

EastGun-A
Novice
856 Views

hello, i wonder about the pcie protocol.

If you request 4096B from memory read, the completion will return 8 of 512B, but according to the avst interface, there is a module that determines whether the completion buffer has received all the completions.
In this module, if the request is not completed because all completions have not come, can CPLD in Rx queue fail to transmit?
(Eight 512B CPLDs must arrive, and only then do they transmit together?) Or are they transmitted one by one after checking only the buffer?

EastGunA_0-1686026592312.png

I'm sorry that I can't speak English well.
Thank you for your reply.

0 Kudos
1 Solution
wchiah
Employee
675 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


View solution in original post

5 Replies
wchiah
Employee
838 Views

Hi,

 

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

 

Best regards,

Wincent_Intel


0 Kudos
EastGun-A
Novice
806 Views

Thanks for answering the question!
I'll be waiting for you!

0 Kudos
wchiah
Employee
771 Views

Hi EastGun,


Please accept my apology for late reply.

In a typical system design, when you request 4096 bytes from memory read, the system may choose to split the request into smaller chunks for efficient processing. In your case, the completion returns 8 chunks of 512 bytes each. The completion buffer is likely used to hold these individual chunks until all of them have arrived.

Regarding the behavior of the CPLD in the Rx (receive) queue, it depends on the system design and the specific implementation. If the system requires all eight 512-byte chunks to be received before transmitting anything, the CPLD may indeed wait until it has received all the completions in the buffer before transmitting them together.


You can enable the RX buffer limit port to control the buffer limit on the CplD packet under page 138

https://www.intel.com/content/www/us/en/docs/programmable/683059/21-1-4-0-0/introduction.html


Let me know if you need any further clarification.


Regards,

Wei Chuan


0 Kudos
wchiah
Employee
688 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


0 Kudos
wchiah
Employee
676 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


Reply