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Altera_Forum
Honored Contributor I
785 Views

PCIe Memory Write Transaction

Hi, 

 

I am facing an issue while performing memory write transaction with payload more than 128Bytes from root to endpoint. Write transaction with less than 128Bytes are completed easily. I have checked the BAR size its 256KB. Maximum payload size is also 2KB (maximum). I have tried almost every thing.... 

 

Can somebody guess what the issue is....
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8 Replies
Altera_Forum
Honored Contributor I
39 Views

I see a similar behavior, I try to transfer 128 bytes, but see two bursts, each 64 byte. 

My guess is it is related to the cache line size. I have set the max payload size to 512 bytes and expected one 128 byte burst. But I see the two 64 byte bursts.  

I use the 64 bit st interface.
Altera_Forum
Honored Contributor I
39 Views

But i am facing some thing different. Whenever i perform 128Bytes write transaction it is received at the avalon side of endpoint correctly, in a single burst. Write transaction with more than 128Bytes payload are entirely not visible at the receive side of endpoint

Altera_Forum
Honored Contributor I
39 Views

From various threads i found that most of the people are using multiple 128Bytes payload to transfer payload more than 128Bytes!!! Is there any restriction that prohibits TLPs with more than 128Bytes payload?????

Altera_Forum
Honored Contributor I
39 Views

128 bytes is the likely limit for a single PCIe memory transfer. 

I don't know if it is a hard limit in the PCIe protocol, or whether the ends can negotiate a different value. 

However it is probably getting near to the point of diminishing returns. 

Remember, a PCIe request is actually an HDLC frame - cannot be actioned until the crc has been checked (etc).
Altera_Forum
Honored Contributor I
39 Views

I think there is a configuration space register that is needed to be programmed otherwise i saw the endpoint example that is generated by megafunction. In their example endpoint is performing much larger memory write transactions.

Altera_Forum
Honored Contributor I
39 Views

Finally i picked out what was wrong..... 

I haven't programmed the device control register. There is a field that indicates the maximum payload transfer in a single TLP and the default value was 3'b000 (i.e. 128Bytes) changing it to 2KB(3'b100) solved my problem.  

 

Thanks to all of you
Altera_Forum
Honored Contributor I
39 Views

Hi guys, 

 

I did a simple write Transaction with C Code under LINUX. 

Please can anybody give me an advice how I can do a simple Read/Write Transaction with VHDL (for example LED turn On/Off) without the need to test under Linux? 

 

Regards,
Altera_Forum
Honored Contributor I
39 Views

can any one plz tell me how to perform simple memory read and write operation . the user guide of pcie is confusing me .