PCIe Memory write TAG

[EastGun-A]

hello, i wonder about the pcie protocol.

i just know memory write request don't need completion. 

then, why tag bit is essential??

is any function in memory write request???

tag bit do the ordering each request??

then additional question is how do pcie ordering about continuous write request?

i mean, If 100 consecutive MWr requests come in, they may not come in order due to a link problem. How do pcie manage the order?

I'm sorry that I can't speak English well.
Thank you for your reply.

[Wincent_Altera]

Hi,

For the tag bit information, I found one article.

It may answer all of your question.

https://www.linkedin.com/pulse/pci-express-primer-3-transaction-layer-simon-southwell/?trk=pulse-article_more-articles_related-content-card

second question.

PCIe ordering rules ensure that all memory transactions, including continuous write requests, are executed in a predictable and reliable manner. The PCIe ordering rules specify how read and write operations should be ordered in time and how they should interact with other transactions on the bus.

For continuous write requests, PCIe ordering guarantees that the data is written to the target memory in the order in which it was sent by the initiator. This is achieved through a combination of various mechanisms such as the Memory Write and Invalidate (MWI) command and the Non-Posted Write (NPW) protocol.

In NPW protocol, the data is written to the target memory without waiting for any acknowledgement from the receiver. The receiver, in turn, sends an acknowledgement once the write operation is complete. The MWI command is used to invalidate the cache lines in the memory hierarchy of the receiving device so that the updated data can be fetched from memory.

Overall, the PCIe ordering rules ensure that all transactions on the bus are executed in the order in which they were issued, regardless of the type of operation or the devices involved. This ensures that continuous write requests are processed in a reliable and predictable manner, without any loss or corruption of data.

Hope this answered your question. let me know if further clarification is needed.

Regards,

Wincent_Intel

[EastGun-A]

Thank you so much for your reply.

Then, in the case of posted memory write, does it matter what the tag bit is?
I wonder if it is possible to arbitrarily change the tag bit for posted memory write.

[Wincent_Altera]

Hi

The tag bit in a posted memory write generally does not affect the behavior or outcome of the write operation itself. The tag bit is typically used for tracking and identifying specific memory regions or access types, but it does not directly impact the actual write operation.

Changing the tag bit for a posted memory write may be possible depending on the system and the specific implementation of the memory controller. However, it is important to note that altering the tag bit arbitrarily could potentially disrupt the memory system's intended behavior and could lead to unpredictable results or errors.

Regards,

Wincent_Intel

[EastGun-A]

Thank you so much for taking the time for me.

In addition, in the avalon streaming interface, the payload limit is 512B and the read request limit is 4096B. Then, is the completion with data created by automatically splitting the TLP into multiple pieces in the P-tile? (I wonder if the address is automatically changed and the TLP is created.)

[Wincent_Altera]

Hi,

In the Avalon streaming interface, the payload limit refers to the maximum size of a single data payload that can be transferred in one transaction, which is 512 bytes. The read request limit, on the other hand, specifies the maximum size of a read request, which is 4096 bytes.

If a read request exceeds the payload limit, it needs to be divided into multiple transactions. This division and subsequent reassembly of the data is typically handled by the Avalon interface itself, or by the hardware or software components connected to it. The address may be automatically adjusted for each transaction to retrieve the appropriate data, and multiple Transaction Layer Packets (TLPs) may be generated to transfer the complete data.

The specific implementation details may vary depending on the design and configuration of the system using the Avalon interface, but the interface itself provides mechanisms to handle larger requests by splitting them into multiple transactions as necessary.

Hope this answered your question.

Regards,
Wincent_Intel

[EastGun-A]

Oh, is there an additional function to correct the order with tag bits when applying relaxed ordering in the posted write request?

[Wincent_Altera · Accepted solution]

Hi,

Based on my understand the answer is No, there is no additional function specifically for correcting the order with tag bits when applying relaxed ordering in a posted write request. The purpose of relaxed ordering is to allow certain reordering of memory operations for improved performance, but it does not involve any specific mechanism to correct the order with tag bits. If you require a specific ordering of memory operations, you should use a different memory ordering model or synchronization techniques such as fences or barriers. Please correct me if you feel I am wrong.

Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[EastGun-A]

Sorry for the late reply.
Thank you so much for answering my question.
have a good day!
I think the forum can be closed! I'll ask another question next time. thank you

[Wincent_Altera]

Hi

Thanks for your confirmation on the answer

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel