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agula
New Contributor I
106 Views

PCIe SRIOV VF capabilities

Hi,

When using virtual functions on the Arria 10 device , I notice that the virtual functions do not have the same maximum read size and maximum payload size as the physical function. Is there a way to change this so that they match. Since they all share the same physical hardware, I would imagine that they would have the same MSS and MPS in configuration space. Not sure if this is the case of not.

Thank you!

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6 Replies
Deshi_Intel
Moderator
90 Views

HI,


Based on what I read from the user guide doc, by right the virtual function register (PCI Express Device Capabilities Register) should be the same between physical function (PF) and virtual function (VF)


So, let's take max payload setting for example


  • page 85 - reg (0x084) - Maximum Payload Size supported by the Function. Can be configured as 000 (128 bytes) or 001 (256 bytes)
  • The setting should follow the max payload setting set in PCIe IP
  • page 24 - the only requirement in max payload setting is just to set setting > 128 if used more than 2 PF


May I know where do you see the setting difference in PF vs VF ?


Thanks.


Regards,

dlim


agula
New Contributor I
83 Views

I received this information through lspci -d 1172: -vv

DevCtl under the PF capabilities shows a MPS of 256 and read request size of 4K.

DevCtl under the VF capabilities shows a MPS of 128 and read request size of 128.

 

I'm more worried about the read request size being that small. Since I need high bandwidth on all virtual functions for network interfaces. 

 

Thanks

Deshi_Intel
Moderator
50 Views

Hi,


Have you review your PCIe software driver to confirm the actual MPS and read request size setting for both PF and VF in PCI Express Device Capabilities Register space ?


Also, what's the MPS setting set in FPGA PCIe hard IP ?


Thanks.


Regards,

dlim


agula
New Contributor I
45 Views

Yes, I have verified that both MPS and maximum read request size are both 0 at address 0x88 of the virtual function driver. The MPS setting of the FPGA PCIe hard IP is set to 2K, which is correctly reflected in device capabilities for both PF and VF.

 

Deshi_Intel
Moderator
17 Views

Hi,


According to user guide page 85 (table 58)


PCI Express Device Control and Status Register - 0x088

  • Value setting of 0 for both MPS bit [7:5] and RRS bit [14:12] is indeed = 128 bytes
  • So did you modify your driver design to change MPS and RRS setting to other larger value beside 0 ?


Another thing to take note is PCI Express Device Capabilities Register -0x084

  • bit [2:0] that control Maximum Payload Size supported by the Function
  • What's the value setting here ?


Thanks.


Regards,

dlim


agula
New Contributor I
9 Views

Hello,

 

I tried to program them but they did not update their values. It seems they are set to read only for the Virtual Function. The MPS value at 0x084 is set to 'b100 reflecting a 2K MPS, which is what it is set in the PCIe IP editor.

 

 

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