Hello,I want simulate, with Modelsim, an Altera PCIe Endpoint design Qsys-Avalon-MM based. I begin starting with the PCIe Qsys example in Chapter 17 of the "IP Compiler for PCI Express User Guide". But I would like to write my own PCIe transactions for the PCIe Root Port BFM. Where is the file in which transactions are defined?. Best regards. Peio
Hi de_prince,The ALTERA simulation environment for PCIe is a little bit strange. Instead of provide standalone BFMs, they are created for each project you launch. One file with more than 170000 lines "altpcietb_bfm_driver.v" (unmanageable) contains the transactions. Moreover, simulations are very, very slow. The good news is that procedures are well documented. I'm absolutely disappointed with the simulation environment, I hope the PCIe silicon is better. I have not checked in silicon jet. Peio
If all you are doing is creating some user logic to decode the TLPs via the Avalon bus, it might just be easier to write your own BFM at the Avalon level with good constrained random testing. Doing this I was able to simulate thousands of TLPs in about a minute. Then I plugged it into a real system and it worked fine!Bare in mind though, my system was just a 16K dual ported memory, so I only cared about reads and writes. The rest of the packets I just ignored or created the "not supported" completion packets.
Hi Tricky,You talk about Avalon-ST interface. I don't want to be a PCIe expert, TLP's, credits, data alignment...and so. The only thing I need, is a plain parallel bus interface, so I discard using Avalon-ST. Although the Avalon-MM is not available as standalone IP using Megawizard (thanks Altera :evil:). Avalon-MM it's the interface I'll use.
The Avalon ST is not that hard to use. The IP core takes care of all of the handshaking, credits etc, you just get the data requests. But yes, you do have to dissasemble/create the packets yourself and follow the rules. The MM interface would be simpler, but you can only use that via QSys.