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RWitt
Beginner
1,413 Views

PCIe a10_hip Several issues: MSI-X conduit/signals not exposed in non-SRIOV mode, no Gen3@8Gbps training (can't get past 5Gbps), Configuration space "capabilities" enabled but not selected in PD, etc.

I have several posts/questions raised on the FPGA Tools community because I assumed I was having issues configuring the PCIe IP in Platform Designer. Just in case this is the better forum I'll raise them again in this single post:

a) with SR-IOV enabled the link won't train at 8Gbps, links-up at 5Gbps. Same core with SR-IOV not enabled works fine. Is/are there control signals I need to toggle/set at the top-level when SR-IOV is enabled?

b) with SR-IOV "not" enabled, and MSI-X "enabled", I can't get the MSI-X conduit/signals exposed to the application layer (note: MSI-X does appear enabled in the PCIe Capabilities Space - enumerated with it enabled). If SR-IOV is turned on (single PF, no VFs) and MSI-X is enabled I get those signals (app_msix_xxxx).

c) with SR-IOV "not" enabled the Virtual Channel capabilities is exposed in the PCIe config space, but I did not enable anything related to VC in Platform Designer.

d) there is another question on this forum about supporting more than 64 non-posted tags when configuring the H-IP for three PFs, please see that one if you think you have an answer for it.

 

Update: 12/04/18 - I was looking into a few of my questions further, some thoughts based on the lettering above:

b) With an Avalon-MM DMA environment selected the MSI-X signals appear at the application layer, along with additional control signals I can see in an errata but not in the manual's signal list (such as msix_control[15:0]).

 

c) it looks like the VSEC is related to the support for CvP. In SR-IOV this capability does not appear to be supported. Also, on another post I see with SR-IOV that the AER capability is always in the config space (I have not checked whether or not the "Enable Advanced Error Reporting" configuration (on/off) affects whether it indicates enabled (supported) or not.

 

More to follow...

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2 Replies
Nathan_R_Intel
Employee
17 Views

Hie,

 

I have answered your questions in the different forum threads. I will copy and paste the answers here as well.

 

a) with SR-IOV enabled the link won't train at 8Gbps, links-up at 5Gbps. Same core with SR-IOV not enabled works fine. Is/are there control signals I need to toggle/set at the top-level when SR-IOV is enabled?

Currently, no particular control signal is required to be toggled or set at top level when SR-IOV enabled. Per your other thread question (https://forums.intel.com/s/question/0D50P000048SUcYSAW/platform-designer-a10-pcie-sriov-wont-run-at-...), I am suspecting you need to enable at least 1 VF if SR-IOV is enabled for the Gen3 equalization registers to be enabled.

 

b) with SR-IOV "not" enabled, and MSI-X "enabled", I can't get the MSI-X conduit/signals exposed to the application layer (note: MSI-X does appear enabled in the PCIe Capabilities Space - enumerated with it enabled). If SR-IOV is turned on (single PF, no VFs) and MSI-X is enabled I get those signals (app_msix_xxxx).

I will answer this question in the other thread you have opened.

(https://forums.intel.com/s/question/0D50P000048SW34/platform-designer-a10-pcie-core-with-sriov-not-e...)

 

 

c) with SR-IOV "not" enabled the Virtual Channel capabilities is exposed in the PCIe config space, but I did not enable anything related to VC in Platform Designer.  I will need more details on which Virtual Channel capabilities are exposed so I could investigate this. Could you help file another forum thread on this as this could require significant amount of time to investigation.

 

 

d) there is another question on this forum about supporting more than 64 non-posted tags when configuring the H-IP for three PFs, please see that one if you think you have an answer for it.

I have answered in the other thread ; mentioning that using multiple PFs does not mean additional non-posted tags can be supported. The 64 is shared between the three.

(https://forums.intel.com/s/question/0D50P000048STeQSAW/platform-designer-a10-pcie-sriov-core-set-for...)

 

b) With an Avalon-MM DMA environment selected the MSI-X signals appear at the application layer, along with additional control signals I can see in an errata but not in the manual's signal list (such as msix_control[15:0]). Could you provide me more details, which device, interface type and Quartus version used, so I could look into this separately. Please  help file another forum thread for this as this could require significant amount of time to investigation.

 

c) it looks like the VSEC is related to the support for CvP. In SR-IOV this capability does not appear to be supported. Also, on another post I see with SR-IOV that the AER capability is always in the config space (I have not checked whether or not the "Enable Advanced Error Reporting" configuration (on/off) affects whether it indicates enabled (supported) or not. I have answered this in the other thread.

(https://forums.intel.com/s/question/0D50P000048SU13SAG/platform-designer-a10-pcie-sriov-enables-aer-...)

 

 

Regards,

Nathan

RWitt
Beginner
17 Views

My update 12/05/18

a) it does not make any sense that you would have to have at least one VF when using the SR-IOV core.

Solution/Answer: I spent the day changing parameters and have found how to link at 8Gbps. In the "Parameters" settings tab, under the "PHY Characteristics" tab I first enabled the "Soft DFE" thinking that would help and it didn't (but I left it selected). I then checked the "Enable RX polarity inversion soft logic" box and enabled that. That was the answer, I successfully linked at 8Gbps. I then built again turning that polarity inversion off and I could only link at 5Gbps. So, there is something about the SR-IOV wrapper that makes the link bring-up different.