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Hello,
I'm using the PCIe hard IP on a Cyclone IV GX device. I enabled MSI-X and configured MSI-X Capabilities using the Megawizard. The actual contents of the implemented capability registers seem to be scrambled somehow. For example, the table size value appears at the LSB of the PBA pointer. Table offset and PBA offset also appear at different places. The "Capability ID" (0x11) and the "Next Pointer" (0x78) are correct however. IP Core Version: 11.1 Build 259 Any help is appreciated. Ralf- Tags:
- PCIe
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