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Altera_Forum
Honored Contributor I
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PCIe link training fails, CV_DE1(rootport) <-> CVGT (endpoint)

Hi All! 

 

I faced with the task to build a PCIe based system. For debugging a rootport part of the system I use Terasic DE1 Cyclone V GX based board equipped with special rootport<->hsmc (x1) daughter card I've developed. 

Altera Cyclone V GT board is used as an endpoint. 

 

I tested duplex data transmission through the link using simple transmitter based projects (2.5GBps). The system works well) 

 

I check ltssmstate to view the current state of both boards when I use PCIe based projects and try to get L0 state.  

 

The problem is that the CVGT board (endpoint) get the state ltssmstate==1 and then 2 on having got the PERSTn from root. At the same time DE1 (rootport) get ltssmstate==1 at first and finally became zero (see attachments). 

How can I debug this? 

 

Thanks in advance!!!
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