FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5989 Discussions

PCIe link training fails, CV_DE1(rootport) <-> CVGT (endpoint)

Altera_Forum
Honored Contributor II
765 Views

Hi All! 

 

I faced with the task to build a PCIe based system. For debugging a rootport part of the system I use Terasic DE1 Cyclone V GX based board equipped with special rootport<->hsmc (x1) daughter card I've developed. 

Altera Cyclone V GT board is used as an endpoint. 

 

I tested duplex data transmission through the link using simple transmitter based projects (2.5GBps). The system works well) 

 

I check ltssmstate to view the current state of both boards when I use PCIe based projects and try to get L0 state.  

 

The problem is that the CVGT board (endpoint) get the state ltssmstate==1 and then 2 on having got the PERSTn from root. At the same time DE1 (rootport) get ltssmstate==1 at first and finally became zero (see attachments). 

How can I debug this? 

 

Thanks in advance!!!
0 Kudos
0 Replies
Reply