We are using the Cyclone V SoC Devkit (5CSXFC6D6F31C7).
We wish to use the PCIe transceiver for the Cyclone V to act as an endpoint, and we would use the whole x4 interface.
Now, we are going to use a proprietary PCIe optical transceiver, that according to the manufacturer, doesn't present a load sufficient to be detected as a receiver when using a common mode pulse on Tx channels (which apparently is part of the PCIe spec). That manufacturer proposes a spoofing circuit that adds some load.
I saw no mention of this PCIe Detect common mode pulse in the PCIe Hard IP documentation.
- Does the PCIe Hard IP implement a receiver detect circuit, besides using the PRSNT# ?
- If it does, can it be disabled / ignored ?
In other words, the PCIe x4 Hard IP, will the Cyclone V try to detect that it is connected to a receiver (on the physical layer only) by any other means than checking the PRSNTx1/PRSNTx4 signals ?