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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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PCIe simulation BFM differs from quartus

Honored Contributor II

I've created an easy testbench for pcie. I’m trying to read and write data to different memory addresses. My design includes RAM memories(dual port alt syncram), and Input/Output PIO ports. Writing/Reading from testbench to the PIO and memories works fine, but when I compile the design it doesn't. I can read data from PCIE in my vhdl, but can't write anything. My task is called io_test. I’m using quartus sopc builder 12.1sp1 and modelsim 10.1b. Arria II Gx Device. I Can't also read anything, written by vhdl, on PCIe side from PIO port enc_out_ctrl. What can I do wrong? My testbench is based on example_pcie testbench. I only added io_test task. I communicate with Aria from linux driver. Dummy BFM master is replaced in design with my Verilog Code. I changed on_chip_ram to allow me simultenously read/write 128bits in Megawizard, it works properly in simulator tough. module dec_din ( // inputs: address, address2, byteenable, byteenable2, chipselect, chipselect2, clk, clken, clken2, reset, write, write2, writedata, writedata2, // outputs: readdata, readdata2 ) ; parameter INIT_FILE = "../dec_din.hex"; output readdata; output readdata2; input address; input address2; input byteenable; input byteenable2; input chipselect; input chipselect2; input clk; input clken; input clken2; input reset; input write; input write2; input writedata; input writedata2; wire readdata; wire readdata2; wire wren; wire wren2; assign wren = chipselect & write & clken; assign wren2 = chipselect2 & write2 & clken2; //s1, which is an e_avalon_slave //s2, which is an e_avalon_slave wire sub_wire0; wire sub_wire1; altsyncram altsyncram_component ( .byteena_a (byteenable), .clock0 (clk), .wren_a (wren), .address_b (address2), .clocken0 (1'b1), .data_b (writedata2), .wren_b (wren2), .address_a (address), .data_a (writedata), .q_a (readdata), .q_b (readdata2), .aclr0 (1'b0), .aclr1 (1'b0), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_b (1'b1), .clock1 (1'b1), .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), .eccstatus (), .rden_a (1'b1), .rden_b (1'b1)); defparam altsyncram_component.address_reg_b = "CLOCK0", altsyncram_component.byte_size = 8, altsyncram_component.clock_enable_input_a = "NORMAL", altsyncram_component.clock_enable_input_b = "NORMAL", altsyncram_component.clock_enable_output_a = "NORMAL", altsyncram_component.clock_enable_output_b = "NORMAL", altsyncram_component.indata_reg_b = "CLOCK0", altsyncram_component.intended_device_family = "Arria II GX", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 128, altsyncram_component.numwords_b = 32, altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_reg_a = "CLOCK0", altsyncram_component.outdata_reg_b = "CLOCK0", altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", altsyncram_component.widthad_a = 7, altsyncram_component.widthad_b = 5, altsyncram_component.width_a = 32, altsyncram_component.width_b = 128, altsyncram_component.width_byteena_a = 4, altsyncram_component.width_byteena_b = 1, altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; endmodule

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