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Altera_Forum
Honored Contributor I
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PCIe

Hi 

 

I have 1 simple design where PCIe x1 (Native endpoint) BAR0 is connected to PCIe CRA and onchip memory and BAR1 is connected to DMA. DMA read However, i have no idea on how to make use of page in PCIE. 

 

e.g. 

I would like to use the DMA to transfer a chunks of data(2MB) from onchip memory to the host system via PCIe. So, I need to configure the DMA on source address, destination address and transfer length. Other than this, what else i should configure? 

 

Besides, i do notice that if use dynamic translation table, i need to configure Avalon-MM-to-PCI Express Address Translation Table via PCIe CRA (0x1000).  

 

In this scenario: 

1. Should i use fixed or dynamic translation table? How to justify? 

2. How to justify the page size and number of address page?  

3. One page of 4MB vs four page of 1MB. What is the pros and cons? 

4. What is the pro and cons if multiple master share the same page? 

5. A2P_ADDR_MAP_LO should be filled with address of Host system, right?  

6. How does it correspond to the avalon address of each avalon master(DMA read and DMA write master)? 

 

Last, i also notice that,i can directly read/write onchip memory without connect to the PCIe.txs.  

 

7. Is that mean, i can read from or write to any slave via PCIe BAR without using the PCIe.txs? 

8. In another word to say, PCIe.txs is only used when avalon master (DMA) need to initiate the transcation to read/write data on the slave (host system), right? 

 

Pls correct me if mistaken. Pls advice. 

 

Thanks.
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1 Reply
Altera_Forum
Honored Contributor I
39 Views

 

--- Quote Start ---  

Hi 

I have 1 simple design where PCIe x1 (Native endpoint) BAR0 is connected to PCIe CRA and onchip memory and BAR1 is connected to DMA. DMA read However, i have no idea on how to make use of page in PCIE. 

 

e.g. 

I would like to use the DMA to transfer a chunks of data(2MB) from onchip memory to the host system via PCIe. So, I need to configure the DMA on source address, destination address and transfer length. Other than this, what else i should configure? 

 

--- Quote End ---  

 

 

When you say 'configure DMA', you mean a DMA controller, right? 

 

BTW, you don't have to use a 3rd party controller, your own logic can drive transfers fairly easily (especially Tx to the host). 

 

 

--- Quote Start ---  

 

Besides, i do notice that if use dynamic translation table, i need to configure Avalon-MM-to-PCI Express Address Translation Table via PCIe CRA (0x1000).  

In this scenario: 

1. Should i use fixed or dynamic translation table? How to justify? 

2. How to justify the page size and number of address page?  

3. One page of 4MB vs four page of 1MB. What is the pros and cons? 

4. What is the pro and cons if multiple master share the same page? 

 

--- Quote End ---  

 

 

These are system implementation details that it's up to you to decide upon. 

 

 

--- Quote Start ---  

 

5. A2P_ADDR_MAP_LO should be filled with address of Host system, right?  

6. How does it correspond to the avalon address of each avalon master(DMA read and DMA write master)? 

 

--- Quote End ---  

 

 

The avalon master address and the host address are two separate address spaces. The address translation table transfers the LSbits from one to the other. 

 

 

--- Quote Start ---  

 

Last, i also notice that,i can directly read/write onchip memory without connect to the PCIe.txs.  

7. Is that mean, i can read from or write to any slave via PCIe BAR without using the PCIe.txs? 

8. In another word to say, PCIe.txs is only used when avalon master (DMA) need to initiate the transcation to read/write data on the slave (host system), right? 

 

--- Quote End ---  

 

 

Yes, but non DMA transfers are relatively very slow. 

 

Also, if you're designing your own DMA engine USE QUARTUS 12.0, 11.1 sp1 had broken interface logic, and 11.0 didn't have working interrupt logic. 

 

 

Nial.
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