PHY S10 configuration: PCS Direct 64 bit without fifo

[AJ]

Hi everyone,

  I need the following configuration for 10G (low latency): PCS Direct, interface width = 64, without tx fifo and rx fifo.

I can't do this configuration for Stratix 10. I have two configuration variants without errors: 64 bit bus and fifo (phy_s10.ip) or 40 bit bus and no fifo (phy_s10_wo_fifo.ip).

How can I get the configuration for PCS Direct with 64 bit bus and without fifo?

  Intel HIP documentation:

    https://www.intel.ru/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf

Best regards, Alex

[AJ]

ip files

[AJ]

Is anybody here?

[KeenYewL_Intel]

Hi Alex, my apologize, I'll find someone to address your question.

[CheePin_C_Intel]

Hi Alex, I would like to apologize for the delay. I have just been assigned to work on this case. Thanks for sharing the .ip files. As I understand it, you encounter some issues when trying to configure the S10 L/H-Tile Native PHY to with PCS Direct interface width = 64 bits and TX/RX core interface FIFO = Register mode. For your information, you would need to enable double rate transfer mode and disable the simplified data interface so that you could achieve the above configuration. Without these, the max PCS direct interface width is only 40 bits with FIFO = Register mode. You may refer to the "Phase Compensation-Register" section in the user guide for further details. In your phy_s10.ip, you can do the following changes: 1. Enable double rate transfer mode 2. Disable the simplified data interface 3. Set TX/RX FIFO = Register and partially full threshold = 5 4. tx/rx_clkout clock source = PCS clkout x2 Please try to see if it works on your side. Please let me know if there is any concern. Thank you. Best regards, Chee Pin