Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Beginner
278 Views

PLL Cascade bandwidth configuration issues (fPLL)

Jump to solution

The documentation and the IP Configuration editor list opposite rules for fPLL cascading. In the documentation about fPLL cascading it says

"Set the source (upstream) fPLL bandwidth to Low setting and the destination (downstream) fPLL bandwidth to High setting."

(Section 3.11.3, Step 6, Intel Arria 10 Transceiver PHY User Guide).

 

Yet when I configure the downstream PLL and select 'Enable downstream cascaded pll' and set the bandwidth to 'high' there is an error message that says "Bandwidth setting must be 'low' when the fPLL is specified as a downstream pll."

 

Which is right? And if it's the documentation, how do I set the downstream fPLL bandwidth high in a cascaded configuration?

 

Note: Quartus Pro 19.2. IP Parameter for fPLL Arria 10.

0 Kudos

Accepted Solutions
Highlighted
28 Views

Hello there, 

 

Apologize for delay in response , I was in Business trip and customer visits.

 

As per my understanding document statement looks correct to me. Downstream PLL is the destination PLL and for cascade operation downstream PLL has to be drive from the source PLL.

Source PLL is driven from the reference clock which shall be low bandwidth , whereas downstream PLL should be High bandwaidth.

 

However, I believe the issue observed is when user selects the option “Enable downsteam cascaded pll”.Also the steps to perform fPLL to fPLL cascading per user guide does not require this option to select. Hence, please unselect it to fix you issue.

Also I get chance to quick check and done few experiment.

i) Uncheck the “Enable Downstream PLL options “ 

Result : Synthesized and Fitter passed, 

Verification : Cascade Source : Fitter Location -:”FPLLREFCLKSELECT_1CT”

            Transceiver pll  : Fitter location : “FPLLREFCLKSELECT_1CB” 

ii) Check the “Enable Downstream PLL options “

Result : Synthesized and Fitter passed. 

Verification : Cascade Source : Fitter Location -:” FPLLREFCLKSELECT_1CT”                   

 Transceiver pll  : Fitter location : “FPLLREFCLKSELECT_1CB”

 

From the result both are same location irrespective of the setting. I didn’t find any other to verify the same.

 

I will raise the internal to the team about “Enable downsteam cascaded pll” in the document and come back to you as soon i can.

 

Sorry again for the delay.

 

Thank you, 

 

Regards,

Sree

View solution in original post

0 Kudos
1 Reply
Highlighted
29 Views

Hello there, 

 

Apologize for delay in response , I was in Business trip and customer visits.

 

As per my understanding document statement looks correct to me. Downstream PLL is the destination PLL and for cascade operation downstream PLL has to be drive from the source PLL.

Source PLL is driven from the reference clock which shall be low bandwidth , whereas downstream PLL should be High bandwaidth.

 

However, I believe the issue observed is when user selects the option “Enable downsteam cascaded pll”.Also the steps to perform fPLL to fPLL cascading per user guide does not require this option to select. Hence, please unselect it to fix you issue.

Also I get chance to quick check and done few experiment.

i) Uncheck the “Enable Downstream PLL options “ 

Result : Synthesized and Fitter passed, 

Verification : Cascade Source : Fitter Location -:”FPLLREFCLKSELECT_1CT”

            Transceiver pll  : Fitter location : “FPLLREFCLKSELECT_1CB” 

ii) Check the “Enable Downstream PLL options “

Result : Synthesized and Fitter passed. 

Verification : Cascade Source : Fitter Location -:” FPLLREFCLKSELECT_1CT”                   

 Transceiver pll  : Fitter location : “FPLLREFCLKSELECT_1CB”

 

From the result both are same location irrespective of the setting. I didn’t find any other to verify the same.

 

I will raise the internal to the team about “Enable downsteam cascaded pll” in the document and come back to you as soon i can.

 

Sorry again for the delay.

 

Thank you, 

 

Regards,

Sree

View solution in original post

0 Kudos