PLL IP Core

[Altera_Forum]

Hi, 

I'm interesting to use clock dividing/multiplication. Use the IP MegaWizard ALTPLL. As i have seen in datasheet, before the MegaWizard function will start work, the asynchronous reset (areset input) have to be done. The Quartus compilation the code was passed, but during ModelSim simulation i got the negative result. The simulation started but automatically stoped (fatal error) the same place where the asynchronous reset for MegaWizard Core was ended. The fatal error message is "floating point exception".   I tried to convert: 50Mhz to 10mhz; 50Mhz to 100Mhz;   The asynchronous reset I'm making by the counter.   what is the reason for the error? Thanks.

[Altera_Forum]

i think all theese happen cause the ALTPLL MegaWizard not succeeded to lock on the incomming freq...why???

[Altera_Forum]

Don't use reset at all. Anyway, converting 50MHz to 10millihertz is impossible in PLL :)

[Altera_Forum]

sorry,it was 10MHz. 

I have tried to simulate without reset, it's running without any error. But output freq is 'X' value logic...as i said bafore i think it's happens because the ALTPLL modul not locked on my incoming freq... I don't know why... I used the default values of the modul, only the incoming and outcoming freqs were changed.

[Altera_Forum]

Well PLL is dedicated device and I doubt You will be able to simulate it successfully.

[Altera_Forum]

But PLL was destined for this purpose. It has to work...

[Altera_Forum]

And in reality - it does.

[Altera_Forum]

So why am I not succeeding?  

My duty is only to provide the incoming freq 50Mhz. There is no place for mistake. Modul works in independence mode.

[Altera_Forum]

If You're getting X on the output, maybe signal has no initial value? That could be a bug also. Probably nobody would simulate PLL core to get higher frequency in the simulation.

[Altera_Forum]

Ok,I'll try.Thanks

[Altera_Forum]

The initial value doesn't solved the problem

[Altera_Forum]

Hmm, reset polarity is also OK? Maybe it requires some setup time, so Your simulation is too short?

[Altera_Forum]

The simulation was running something like 30 min...the "locked" output stayed on "0" logic. PLL can't lock the phase i think.

[Altera_Forum]

Eurika!!! 

The problem is a result of time definition in ModelSim. I have taken "NanoSeconds" as time definition. But for 50MHz we have to take the "PicoSeconds". In other words, the ALTTTL modul and high entity were working if I was burn it into the FLASH memory of the development board.