- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hallo Everyone
I am making a Parallel Flash Loader (PFL) IP core for MAX V device. I have some problems in constraining the design with the timing. In the following link it is mentioned that https://www.altera.com/documentation/sss1411439280066.html#sss1458191622012 the following paths should be set as False Path pfl_flash_access_request flash_nce flash_noe flash_nwe flash_data flash_addr but when i set them as false path, the design is not fully constrained. The time quest analyzer shows that this parts are partly constrained and suggest to add an output delay. I wrote the SDC file in the attachment. Can any one give me any suggestion or solutions on what might be wrong here or if my SDC file is correct?Link Copied
4 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
What path(s) does the timing analyzer say are considered unconstrained? There's no way to tell what's wrong by looking at just the .sdc file.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hallo sstrell
Thanks for your reply. For Example if set the flash_nce path as false path, as suggested in the pfl user guide, on the time constrains report it shows that flash_nce path is partially constrained. I am attaching the screen shots of the timing analyzer report that i get when i set the flash_nce as a false path. Setting the other paths mentioned in first post also produces same kind of behavior. I am also attaching the report from the timing analyzer. You can open the file with notepad. Let me know if this information is enough for you, to find the problem or you need some more information.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I don't understand why you're doing this:
set_false_path -from [get_clocks *] -to [get_ports {flash_nce}] It should be simply: set_false_path -to [get_ports {flash_nce}] Same with all your output false paths.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks a lot for your reply. This solves the problem. So if i understood you correctly
output false paths should be set with the command set_false_path -to input false paths should be set with the command set_false_path -from I tried this two command on my input and output ports false paths and it works.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page