Parallel Flash Loader doesn't recognize CFI Flash

[EGrün]

Hi,

I developed a custom hardware with Cyclone V GT and MAX10 FPGAs on board. The MAX10 has to configure the Cyclone V GT via FPP x8 mode out of a CFI-Flash device MT28EW01GABA1LPC-0SIT. Basically the same topology like on your Cyclone 10 GX development kit. The only difference to your Cyclone 10 GX development kit is that I am using only one flash device with 16x databus and I am using FPPx8 configuration mode.

The flash is working fine when I am accessing it via Generic Tri-State Controller.

I did several tests:

- Tests are done without Generic Tri-State Controller in MAX10! Thus there is no bus-conflict to flash device between PFL and Generic Tri-State Controller.

- I created two different PFL designs. One has basic PFL only. The second is your Cyclone 10 GX development kit system_max10 example which I adapted to my above explained hardware.

1.) When I want to access the flash via PFL and Quartus Programmer via JTAG I get the error "Error (18591): Can't recognize the Flash device that attached to device 1. The Flash device is not supported by Quartus Prime software.".

(JTAG chain to both FPGAs work fine)

2.) When I try to configure Cyclone V GT out of the flash this process fails too.

In this case I programmed configuration data previously via Generic Tri-State Controller to flash and then I replaced MAX10 design with above mentioned PFL designs.

I did some analysis with Signal Tap Logic Analyzer:

- PFL does accessing flash on the right flash-address (Option bits). First at offset 0x80 (byte address) the .pof version (in my case 0x03). Second is at offset 0x00 the Page 0 start address. I can see right data and addresses on flash bus in Signal Tap. The PFL state machine (alt_pfl_cfg3_control.v) shows states CFG_NSTATUS_WAIT then CFG_PRE_VERSION then CFG_LOAD_VERSION then CFG_VERSION then CFG_VERSION_DUMMY then CFG_PRE_OPTION then CFG_LOAD_OPTION then CFG_OPTION then CFG_OPTION_DUMMY. After state CFG_OPTION_DUMMY the state machine goes into state CFG_ERROR!

For me it looks like PFL doesn't fetch Option Bits data because I do not see any aktiv reg version2, version3 or version4 in alt_pfl_cfg3_control.v and I do not see any data on data_reg[7..0] or data_out[7..0] in alt_pfl_down_converter.v when I sample these signals with Signal Tap!

Do you have any idea? Are there any known issues relating to PFL in conjunction with CFI-Flash device MT28EW01GABA1LPC-0SIT?

Kind regards.

[YuanLi_S_Intel]

hi, just want to clarify. You were testing with 2 PFL design (your own design & design adopted from our development kit) right? What about the PFL design from the development kit? is it working fine?

[EGrün]

Hi,

Yes I tested with 2 PFL designs as mentioned above. Both designs dosn't work. Both designs have the same behavior as I mentioned at paragraphs 1.) and 2.).

[YuanLi_S_Intel]

Yes, this flash is not supported by the PFL IP.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an386.pdf#page=2

[EGrün]

I don't agree with you! Your posted link is a link to a old user guide V4 which is out of date (2014.06.30). I refer to user guides which mention this flash device since 2018.08.06, Quartus V17.1:

https://d2pgu9s4sfmw1s.cloudfront.net/DITA-technical-publications/PROD/PSG/ug_pfl-17-1-683698-705290.pdf?Expires=1643193673&Key-Pair-Id=APKAJKRNIMMSNYXST6UA&Signature=g6PwZRpZ~q9P1DcdXtzwCiEOg9cgnGQWkVbNzRbX~SQEosX2ZpcEgfuVFht1FO2xONX0qrgvTLhNt9oQJcGucSq1JSJyw5nDxhbNHHDJ4yYHHycZUv9NndJ5z7cN6fgYymghWqLyfK4WV956p26Njjwh55bY2vKW1XbASXPyjoqJwjI6RQPhDWC...

Ich stimme dir nicht zu! Ihr geposteter Link ist ein Link zu einem alten Benutzerhandbuch V4, das veraltet ist (2014.06.30). Ich beziehe mich auf Benutzerhandbücher, die dieses Flash-Gerät seit dem 06.08.2018, Quartus V17.1, erwähnen:


https://d2pgu9s4sfmw1s.cloudfront.net/DITA-technical-publications/PROD/PSG/ug_pfl-17-1-683698-705290.pdf?Expires=1643193673&Key-Pair-Id=APKAJKRNIMMSNYXST6UA&Signature=g6PwZRpZ~q9P1DcdXtzwCiEOg9cgnGQWkVbNzRbX~SQEosX2ZpcEgfuVFht1FO2xONX0qrgvTLhNt9oQJcGucSq1JSJyw5nDxhbNHHDJ4yYHHycZUv9NndJ5z7cN6fgYymghWqLyfK4WV956p26Njjwh55bY2vKW1XbASXPyjoqJwjI6RQPhDWC... EZfLEtD3n0-WBEDr3uIrv-F1Dh1hoczZRccV8pMeKRd~FVEqzql8DBIMIJMXgm-Fv1LMcbU9OOn1gsa5teadpTPSlzp8U-H70DxDLKkLSQfRUXw44Kxtjl5hpySfa5kT~n40A__

[YuanLi_S_Intel]

Yes, you are right. Since it is not working with “system_max10” as well, the potential issue could be due to bitstream generation (POF) or the connection between MAX10, Cyclone V GT and CFI-Flash.

But first thing first, for the error you obtain during programming the POF with programmer, can you show me the screenshot of the programmer? Moreover, during POF file generation, have you selected the correct part number for the flash?

[EGrün]

Thank you for response.

1.) Attached you see a screenshot of the programmer. The MAX10 design with PFL was downloaded before. Screenshot was made with Quartus Webedition, but with Standardedition there is the same message.

Message:

Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
Error (18591): Can't recognize the Flash device that attached to device 1. The Flash device is not supported by Quartus Prime software.
Error (209012): Operation failed

2.) POF file generation:

I attached a screenshot (POF_ file_generation.jpg). I selected standard CFI_1Gb for configuration device.

Additionally I attached the COF file UCX_CVGT__MAX10_PFL_new.zip. You can open the conversion setup data in programming file converter.

[YuanLi_S_Intel]

Since you are using MT28EW01GABA1LPC-0SIT, can you select MT28 instead of CFI in convert programming file?

[EGrün]

I cannot find a MT28 device in Convert Programming File tool. Only MT25 devices are listed, but MT25 devices are QSPI devices.

[YuanLi_S_Intel]

Ok. What about the following? Can you check and see?

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/msgs/msgs/epgme_device_siid_error.htm

Also, can you share me the schematic connection between flash, max 10 and FPGA? You can share me via private message.

[EGrün]

How can I share you via private message?

[YuanLi_S_Intel]

I have already PM you. Please check.

Please let me know if you have tried and check the list as stated in previous reply.

[EGrün]

I replied the checked list via the private message.

[YuanLi_S_Intel]

I am glad that the issue is solved now. Turns out that the issue is due to pin connection setting on the Quartus.