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BrianWissel
Beginner
202 Views

Parallel Flash Loader

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We are using a MAX10 to configure an Arria V, serving as the bridge between Arria V and the 4 memory devices.  I have noticed the fpga_nconfig is not being pulled low to initiate configuration but the Arria V is still being configured.

The device is configured at power up, is there something in the IP that allows configuration to take place at power up without fpga_nconfig?

Attached is a scope capture of fpga_nstatus (bottom trace) and fpga_nconfig (top trace) at power on.

The version of altparallel_flash_loader is WM1.0.

Thanks.

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YuanLi_S_Intel
Employee
171 Views

Yes, you are right.


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3 Replies
YuanLi_S_Intel
Employee
195 Views

Hi Brian,


Are you referring to Arria V's nCONFIG pin right? As per the user guide, it needs to be pulled high for configuration.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_5v2.pdf *Page 280)


Thank You


BrianWissel
Beginner
191 Views

YuanLi_S,

Yes I am referring to the Arria V nConfig pin.

I just want to confirm correct operation as the nConfig pin is never "released" high by the PFL engine, rather it rises with the power supply and stays high.  I just want to confirm that this is correct, reference my attachment in my original post.

Thanks,

Brian

YuanLi_S_Intel
Employee
172 Views

Yes, you are right.


View solution in original post

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