I have a specific block in my design which is set to be of type "Reconfigurable" and is placed on "Fixed/Locked" (Fixed with expansion 1) Logic lock region.
The PR controller ip is "Partial Reconfiguration Controller Intel Arria10/Cyclone 10 FPGA IP", and its connected to a 60mhz clk (from a pll)
rest of the signals are not being usedf (only sampled with signaltap)
The PR ip is configured to be an internal host, with jtag debug mode enabled, avalon-mm slave interface disabled, freeze interface is enabled but currently not connected to anuthing, hierarchical PR support is enabled, and Enabled bitstream compatibility is also enabled.
input data width is 32, clock-to-data ratio is 1, divide error detection frequency is set to 2.
enhanced decompression is disabled.
auto instantiate blocks are both enabled and the generate timing constaints file is also enabled.
the entire flow seems to work just fine, and im getting both sof,jic and rbf file for the partition (using switch GENERATE_PR_RBF_FILE ON)
after loading the sof file into the fpga, when i try to perform the PR to the same partition, im getting both PR_DONE timed out and bitstream incompatible errors.
What could i be doing wrong?
It's hard to figure out what could be going on here, so I'd first say to compare your design and flow to the hierarchical PR tutorial app note and see if you've missed anything or set up anything incorrectly:
If you find anything (or not) post back here.
May I know how do you program the PR RBF file into the FPGA? May I know which Quartus version are you using? Have you try the example design from https://www.intel.com/content/www/us/en/programmable/documentation/ihj1482170009390.html?