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In Xilinx, the completion of a request is denoted by a specific bit in the RC descriptor, while in Intel, there is no analogous bit to indicate the conclusion of the last completion packet in a read request. How can these differences be correlated?
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Hi @thanavignesh,
Thanks for reaching out to the Intel Community.
Please allow me some time to investigate your issue. I’ll follow up with my findings.
Thank you for your patience.
Best Regards,
VenTing_Intel
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Hi @thanavignesh,
Thank you for your patience.
Yes, there is no specific bit to indicate the last completion TLP in a read request.
You may check out the Section (A.2. TLP Packet Formats with Data Payload) in User Guide below to find out the Completion with Data TLP packet format.
Intel Aria 10 and Intel Cyclone 10 GX AVST User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/tlp-packet-formats-with-data-payload.html
I hope these answer your inquiry.
Thanks.
Best Regards,
VenTing_Intel
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Hi @thanavignesh,
May I know if you have further questions regarding this case?
I'm hoping to hear from you soon.
Thanks.
Best Regards,
VenTing_Intel
p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate the survey 4/5.
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Hi @thanavignesh,
We have not received any response from you on the previous answer that we provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.
After 15 days, this thread will be transitioned to community support.
The community users will be able to help you with your follow-up questions.
If you feel your support experience was less than a 9 or 10, please allow me to correct it before closing, or please let me know the cause so that I may improve your future support experience.
Thanks.
Best Regards,
VenTing_Intel

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