Pin Assignment Error

[Altera_Forum]

Hi, 

 Can anyone help me with this error in quartus. I am using DDR2 memory with EP3C120F780C7 DDR2: U25 and U26 bottom chip  I think there is some problem with the pin assignment to the memory pins.I have assigned the pins as mentioned in the manual.  Is there any other reason for the error?  Error: Cannot place pin mem_dq[0] to location AG22  Error: Can't place VREF pin AC18 (VREFGROUP_B4_N1) for pin mem_dq[0] of type bi directional with SSTL-18 Class I I/O standard at location AG22  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 4 when the VREF pin AC18 (VREFGROUP_B4_N1) is used on device EP3C120F780C7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out Info: Location AG19 (pad PAD_219): Pin led[6] of type output uses 1.8 V I/O standard Info: Location AH19 (pad PAD_220): Pin mem_dm[0] of type output uses SSTL-18 Class I I/O standard Info: Location AC17 (pad PAD_221): Pin led[5] of type output uses 1.8 V I/O standard Info: Location AF18 (pad PAD_226): Pin led[2] of type output uses 1.8 V I/O standard Info: Following 1 pins have the same output enable group -6: 1 pins require VREF pin and 1 pins could be output Info: Location AD17 (pad PAD_222): Pin mem_dq[4] of type bi-directional uses SSTL-18 Class I I/O standard Info: Following 1 pins have the same output enable group -7: 1 pins require VREF pin and 1 pins could be output Info: Location AG21 (pad PAD_223): Pin mem_dq[3] of type bi-directional uses SSTL-18 Class I I/O standard Info: Following 1 pins have the same output enable group -9: 1 pins require VREF pin and 1 pins could be output Info: Location AH21 (pad PAD_224): Pin mem_dq[1] of type bi-directional uses SSTL-18 Class I I/O standard Info: Following 1 pins have the same output enable group -2: 1 pins require VREF pin and 1 pins could be output Info: Location AE18 (pad PAD_225): Pin mem_dqs[0] of type bi-directional uses SSTL-18 Class I I/O standard Info: Following 1 pins have the same output enable group -8: 1 pins require VREF pin and 1 pins could be output Info: Location AH22 (pad PAD_228): Pin mem_dq[2] of type bi-directional uses SSTL-18 Class I I/O standard Info: Following 1 pins have the same output enable group -5: 1 pins require VREF pin and 1 pins could be output Info: Location AH23 (pad PAD_230): Pin mem_dq[5] of type bi-directional uses SSTL-18 Class I I/O standard Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed Info: Location AG19 (pad PAD_219): Pin led[6] of type output uses 1.8 V I/O standard Info: Location AH19 (pad PAD_220): Pin mem_dm[0] of type output uses SSTL-18 Class I I/O standard Info: Location AC17 (pad PAD_221): Pin led[5] of type output uses 1.8 V I/O standard Info: Location AD17 (pad PAD_222): Pin mem_dq[4] of type bi-directional uses SSTL-18 Class I I/O standard Info: Location AG21 (pad PAD_223): Pin mem_dq[3] of type bi-directional uses SSTL-18 Class I I/O standard Info: Location AH21 (pad PAD_224): Pin mem_dq[1] of type bi-directional uses SSTL-18 Class I I/O standard Info: Location AE18 (pad PAD_225): Pin mem_dqs[0] of type bi-directional uses SSTL-18 Class I I/O standard Info: Location AF18 (pad PAD_226): Pin led[2] of type output uses 1.8 V I/O standard Info: Location AG22 (pad PAD_227): unused (but has pin assignment of mem_dq[0]) Info: Location AH22 (pad PAD_228): Pin mem_dq[2] of type bi-directional uses SSTL-18 Class I I/O standard Info: Location AG23 (pad PAD_229): unused  Info: Location AH23 (pad PAD_230): Pin mem_dq[5] of type bi-directional uses SSTL-18 Class I I/O standard  :eek:

[Altera_Forum]

does someone know how to solve this problem?  

I meet the same one.

[Altera_Forum]

Hi,go to the pin assignment editor and then group the pins which give error.or see the pin assignment editor of the sample design.You will know it or Read the documentation of the pin assignment and Vref group to solve it.. 

 I did it that way..

[Altera_Forum]

thanks 

I use this and post here, it may be useful for others set_instance_assignment -name OUTPUT_ENABLE_GROUP 75442403 -to DDR7_WE(all signals located in the same BANK are constrained like this) 75442403 is value, it is different for different BANK, and can be defined as you want

[Altera_Forum]

Hi, 

 I git quite the same problem:  -Error: Can't place VREF pin AC18 (VREFGROUP_B4_N1) for pin dq[0] of type bi-directional with 1.8-V HSTL Class I I/O standard at location AG22 - Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 4 when the VREF pin AC18 (VREFGROUP_B4_N1) is used on device EP3C120F780C7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out  Info: Location AG19 (pad PAD_219): Pin LED[6] of type output uses 1.8-V HSTL Class I I/O standard  Info: Location AH19 (pad PAD_220): Pin dm[0] of type output uses 1.8-V HSTL Class I I/O standard  Info: Location AC17 (pad PAD_221): Pin LED[5] of type output uses 1.8-V HSTL Class I I/O standard  Info: Location AF18 (pad PAD_226): Pin LED[2] of type output uses 1.8-V HSTL Class I I/O standard  Info: Following 1 pins have the same output enable group -26: 1 pins require VREF pin and 1 pins could be output  Info: Location AG18 (pad PAD_217): Pin dq[8] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Following 1 pins have the same output enable group -24: 1 pins require VREF pin and 1 pins could be output  Info: Location AH18 (pad PAD_218): Pin dq[10] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Following 1 pins have the same output enable group -30: 1 pins require VREF pin and 1 pins could be output  Info: Location AD17 (pad PAD_222): Pin dq[4] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Following 1 pins have the same output enable group -31: 1 pins require VREF pin and 1 pins could be output  Info: Location AG21 (pad PAD_223): Pin dq[3] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Following 1 pins have the same output enable group -33: 1 pins require VREF pin and 1 pins could be output  Info: Location AH21 (pad PAD_224): Pin dq[1] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Following 1 pins have the same output enable group -32: 1 pins require VREF pin and 1 pins could be output  Info: Location AH22 (pad PAD_228): Pin dq[2] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed  Info: Location AG18 (pad PAD_217): Pin dq[8] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Location AH18 (pad PAD_218): Pin dq[10] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Location AG19 (pad PAD_219): Pin LED[6] of type output uses 1.8-V HSTL Class I I/O standard  Info: Location AH19 (pad PAD_220): Pin dm[0] of type output uses 1.8-V HSTL Class I I/O standard  Info: Location AC17 (pad PAD_221): Pin LED[5] of type output uses 1.8-V HSTL Class I I/O standard  Info: Location AD17 (pad PAD_222): Pin dq[4] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Location AG21 (pad PAD_223): Pin dq[3] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Location AH21 (pad PAD_224): Pin dq[1] of type bi-directional uses 1.8-V HSTL Class I I/O standard  Info: Location AE18 (pad PAD_225): unused (but has pin assignment of dqs[0])  Info: Location AF18 (pad PAD_226): Pin LED[2] of type output uses 1.8-V HSTL Class I I/O standard  Info: Location AG22 (pad PAD_227): unused (but has pin assignment of dq[0])  Info: Location AH22 (pad PAD_228): Pin dq[2] of type bi-directional uses 1.8-V HSTL Class I I/O standard   I just try to build a group to put all the error assignments in but it doesn´t work. Have somebody an idea how i can handle it?  Thanks for your reply!

[Altera_Forum]

Hi, 

 I got a solution.   You just have to add in the Pin Planner a new Column to the Groups and assign a interger variable to that group where the pins which cause this error.  See also Altera 5. I/O Management And here take a look at the following part:  Optimizing I/O Assignment Analysis with Output Enable Group Logic Option Assignments

[Altera_Forum]

in quartus, go to Assignment editor Select your pins, for them, choose option Output Enable Group. make it's value 0 (don't forget Enable value 'Yes'). compile. -bless me :) , smile and be happy.