Pin Delays for Intel Cyclone 10 GX

[TonyCosentino]

I need to find out if the Intel Cyclone 10 GX FPGA has a published pin delays to support DDR wiring.

[sstrell]

You can check the spec estimator to see if C10GX supports what you want/need:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html

[TonyCosentino]

The spec estimator simply showed the cyclone  device specs but no details on the DDR3 routing requirements for the Cyclone 10CX220 device. My question is very specific - Does the Cyclone 10CX220 device have internal pin delays that need to be considered when routing DDR3 on the PCB design? Or are all of the internal timing differences for matched lengths between clocks, command, address, strobes and data internally adjusted?

Best regards,

Tony Cosentino

919-414-2083 cell

Tony@betterboards.com  

[sstrell]

When you parameterize the EMIF IP, you provide information to the tool to minimize skew based on board simulations.  You can choose whether the skew adjustments are performed in the device or that you will be matching delays in your board design.  See this online training and the Board tab of the EMIF IP parameter editor for details:

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html

[AminT_Intel]

Hello Tony,

Is there any update on your end? I will close this case in 3 days if there no update.

Thanks

[AminT_Intel]

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.