Platform Designer and DSP Builder

[Bishnu]

Hi Intel Community, 
I have a query about how Platform Designer works with DSP Builder. For example: 
I have an example design for DSP builder for FFT in Quartus itself. When I run DSP builder and Quartus simultaneously, no matter what, I can't get the .qsys file. However, I can get .tcl files.
Does anyone have some tutorial notes and instructions describing how this system works? I am reading the User Guide, but it is difficult to understand.

Ubuntu 24.1

Arria 10 
Quartus Prime Pro 24.1 
DSP Builder R2024b.

[Bishnu]

Hi all, 
I have found my answer. In Quartus Prime Pro 24.1, the platform designer itself doesn't create a .qsys file; we have to manually create it, which can be named as you desire, but better to give the name as .qsf or .qpf files. 

[sstrell]

Yes, .qsys is the design file format for PD.  But what do you mean by "but better to give the name as .qsf or .qpf files"?

[Bishnu]

Nothing serious.. That's my naming convention. I usually prefer to give the same name as the .qfp file. For example: 
For the sstrell.qpf file, I would like to give it to Sstrell.qsys file for PD. I am very naive to these Intel and Altera platforms. If you have some notes describing how this system works, it would be very helpful. My primary target is the DSP builder. 

[sstrell]

You really only want to do something like that if the PD system will be the top-level design entity for your project.  And of course, if you have other .qsys files for other systems in the design, they need unique names.

.qpf is your main project file and its name gets set when you create the project, usually with the New Project Wizard.  You can set the top-level entity name in the New Project Wizard as well (so it can be unique from the project name) or change it later.

[Bishnu]

Hi sstrell,
I am listening bunch of Altera tutorials about PD, and as usual, they are not that detailed. I don't know why they bother to show examples. So far, I know that PD can help us design a circuit by connecting various IPs, clocks, blocks and etc. 
I am playing around with this PD. I have some DSP builder models, i simulate it in Matlab/DSP Builder, then run the .qpf (Toplevel entity) file in Quartus. I go a lot of files. Then i created a .qsys file, and opened it in PD. It gives me clk_in and reset_in interfaces GUI. 
How can i move forward after this? Adding IPs and so on or making a complete design. 
Thank you 

[sstrell]

You have to build the system design in PD.  Your screenshot is what you get with a brand new .qsys file: clock and reset bridges for bringing a clock and reset into the system.  Read the user guide: https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1/faq.html.

Watch these trainings: https://learning.intel.com/Developer/learn/courses/389/creating-a-system-design-with-platform-designer-getting-started, https://learning.intel.com/Developer/learn/courses/390/creating-a-system-design-with-platform-designer-finish-the-system

[Bishnu]

Hi Sstrell, 
That means I have to make the system from scratch, including adding IPs and all. I design a model in DSP Builder, I run it, and get a .qpf file generated by DSP Builder. I create a .qsys file for the .qpf file generated by DSP Builder example for FFT. And, I created a board XML file. Yes, I got the same GUI interface, only clk and resets. I think now I have to add IPs and all and make a connection between the IPs, and run it in an FPGA. By default, there are clk and resets. I can add the IP i designed from DSP Builder, generate files from this platform designer, and compile it in Quartus to get a bitstream. So fat this is my understanding.