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Honored Contributor I
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Possible Bug in IP Compiler for PCI express 128-bit itnterface

Hi All, 

 

We've run into a problem on the 128-bit IP Compiler for PCI express.  

 

According to our tests, the bug is on the TX side of the Gen2 x8 interface for Stratix IV devices. This may apply to Cyclone IV and Arria II devices, but we can't test those. On TX interface, the FPGA sends out packets using an avalon streaming interface. Altera dictates that any data in packets (RX or TX) must be 64-bit aligned to facilitate memory devices. This means a blank must be inserted when address of the request/completion and the header size meet certain conditions. You can read a description on page 5-8 and page 5-18 of the IP Compiler for PCI Express document. 

 

 

The Gen1 x8 interface (64-bit) obeys this requirement on the RX and TX interfaces, as we'd expect from the specification. The Gen2 x8 interface RX side obeys this alignment requirement as well, however, the Gen2 x8 TX interface does NOT; If a packet is sent by the FPGA with a "blank" to align data, the PCIe core will enter an error state. As a consequence, the device will not be enumerated correctly in LSPCI, where it shows "Unknown header type 7f" and all reads/writes to the FPGA will fail. 

 

This leads us to believe there is a bug in the Q-Word alignment logic provided by altera. Can anyone else confirm this? 

 

Thanks
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Highlighted
Honored Contributor I
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Can't say anything about that version, there. I have worked on a block using Avalon ST Stratix IV (Gen2 x8 128 bit) and V (Gen3 x8 256 bit) and the alignment worked as stated in the manual, for both RX and TX, CplD or MWr requests. I did simulate also using a Cyclone IV IP, the highest rate supported by Quartus at the time and did not see any problem. 

Just make sure you watch two details that caught us all the time. First the CplD lower address is in bytes and therefore you have to drop the first two bits of the address. The alignment counts on bit 2. The MWr requests are in DW addressing (if you defined the two lower bits as reserved as stated in the spec). Of course, also the MWr matters if it is 64 bit or 32 bit addressing, but the CplD always have 3DW headers so it is like they were always 32 bit addressing.
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