Presentation of the Avalon-MM CV HIP for PCIe?

[Zarquin]

Dear community,

I'm confused about this figure from the ug_c5_pcie_avmm.pdf:
What is depicted here? Are these the inputs and outputs of the (1) Avalon-MM CV Hard IP for PCI Express IP core or are these, as the picture title suggests, only the entrances and exits of the (2) CRA -  according to my understanding, the cra slave signals are only the signals of the upper left corner. Or are these the inputs and outputs to and from the (3) Application Layer as the box labelling suggests - in my opinion, at least the PIPE interface  and tx_out and rx_in serial signals and the do not lead to the application layer, (the latter to the pcie lanes)?

So So what is being depicted in the figure below (1), (2) or (3)?

Figure:

[Wincent_Altera]

Hi,

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best regards,

Wincent_C_Intel

[Wincent_Altera]

Hi,

Apologize for late reply, if referring to the picture you sent.

the BLUE arrow means for simulation purposes only.

Hope this answer your question, let me know if you have any other thoughts.

Regards,

Wincent_C_Intel

[Zarquin]

Hello Wincent,

thank you for your effort, but it really doesn't help me, because that wasn't my question.

Regards

Zarquin

[Wincent_Altera]

Hi,

Thanks for your feedback, I try to answer in detail one by one based on my understanding.

What is depicted here? Are these the inputs and outputs of the (1) Avalon-MM CV Hard IP for PCI Express IP core or are these, as the picture title suggests, only the entrances and exits of the (2) CRA - 

• Yes, the block diagram mentions the inputs and output of AVMM IP core of but The optional CRA port for the full-featured IP core allows upstream PCI Express devices and external Avalon-MM masters to access internal control and status registers. Both Endpoint and Root Port applications can use the CRA interface.

according to my understanding, the cra slave signals are only the signals of the upper left corner. Or are these the inputs and outputs to and from the 

• Yes, those input and output are from application layer in big picture, but it might also connected with other block diagram as well you may refer the detail of routing using RTL viewer in Quartus

(3) Application Layer as the box labelling suggests - in my opinion, at least the PIPE interface and tx_out and rx_in serial signals and the do not lead to the application layer, (the latter to the pcie lanes)?

• the BLUE arrow means for simulation purposes only. This is a 32-bit parallel interface between the PCIe IP Core and PHY. It carries the TLP data before it is serialized. It is available for simulation only and provides more visibility for debugging.Note: You cannot change the width of the PIPE interface.

Let me know if you need any further clarification or I miss understanding anything.

Regards,

Wincent_C_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you on this case. Do you still have further inquiries on this issue? I will remain this loop open for 3 days.

If we do not receive any response from you to the previous answer that I have provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

Wincent_C_Intel

[Zarquin]

Hello Wincent_C_Intel,

thank you very much for your reply!

Is there a signal among the blue pipe signals that indicates the end or the beginning of a TLP package?

Best Regards

[Wincent_Altera]

Hi,

The blue pipe signals carry the TLP data before it is serialized.

It is a 32-bit parallel interface between the PCIe IP Core and PHY

It is available for simulation only and provides more visibility for debugging.

Regards,

Wincent_C_Intel