FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

Problem about Tse loop back .

Honored Contributor II

I use sgdmatx Tse sgdmarx test system. Tse set 32bit boundary loop back . I can receive data .for example. Tx data is Ethernet frame 00 00 ff ff ff ff ff ff ...... Receive data is 00 00 ff ff ff ff ff ff ..... The two zero bytes of txdata is for alignment . My question is if I did not set loop back ,the two zero bytes will be sent to rgmii as part of frame data?

0 Kudos
0 Replies